diff options
Diffstat (limited to 'zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7')
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 deleted file mode 100644 index 3c59d5405e..0000000000 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 +++ /dev/null @@ -1,53 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# -# This file defines the correct defaults when using the NPCX7 series chipset -# - -if SOC_SERIES_NPCX7 - -# -# NPCX796FB: 1024 KiB Flash, 192 KiB code RAM, 62 KiB data RAM -# NPCX796FC: 512 KiB Flash, 192 KiB code RAM, 62 KiB data RAM -# NPCX797FC: 512 KiB Flash, 320 KiB code RAM, 62 KiB data RAM -# - -# Code RAM base for NPCX7 series -config CROS_EC_PROGRAM_MEMORY_BASE - default 0x10090000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC - default 0x10070000 if SOC_NPCX7M7FC - -config CROS_EC_RAM_BASE - default 0x200c0000 - -config CROS_EC_DATA_RAM_SIZE - default 0x00010000 - -config CROS_EC_RAM_SIZE - default 0x0000f800 - -config FLASH_SIZE - default 1024 if SOC_NPCX7M6FB - default 512 if SOC_NPCX7M6FC || SOC_NPCX7M7FC - -config CROS_EC_RO_MEM_OFF - default 0x0 - -# NPCX796FB/NPCX796FC: Image size limited by code RAM size (192 KiB) -# NPCX797FC: Image size limited by 1/2 Flash size (256 KiB) -config CROS_EC_RO_SIZE - default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC - default 0x40000 if SOC_NPCX7M7FC - -# RW firmware in program memory - Identical to RO, only one image loaded at a -# time. -config CROS_EC_RW_MEM_OFF - default 0x0 - -config CROS_EC_RW_SIZE - default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC - default 0x40000 if SOC_NPCX7M7FC - -endif # SOC_SERIES_NPCX7 |