diff options
Diffstat (limited to 'zephyr/app/ec/chip')
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx | 53 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 | 53 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 | 51 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 | 41 |
4 files changed, 0 insertions, 198 deletions
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx deleted file mode 100644 index 2da9252775..0000000000 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx +++ /dev/null @@ -1,53 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# -# This file defines the default config values shared by all NPCX chipsets -# - -if SOC_FAMILY_NPCX - -# Enable NPCX firmware header generator -config NPCX_HEADER - default y - -choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE - default NPCX_HEADER_SPI_MAX_CLOCK_50 -endchoice - -choice NPCX_HEADER_SPI_READ_MODE_CHOICE - default NPCX_HEADER_SPI_READ_MODE_DUAL -endchoice - -choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE - default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2 -endchoice - -# ADC -# The resolution and oversamplig values are fixed by the NPCX ADC driver -config PLATFORM_EC_ADC_RESOLUTION - default 10 - -config PLATFORM_EC_ADC_OVERSAMPLING - default 0 - -# Set the system clock to 15MHz. -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 15000000 - -if WATCHDOG - -# Set the delay time for printing panic data. -# 1 cycle is about 32ms. 500ms is about 16 cycles. -config WDT_NPCX_DELAY_CYCLES - default 16 - -endif # WATCHDOG - -# The maximum supported time the NPCX can spend in deep-sleep with instant -# wake is 200 ms, so the hook tick interval is set to match. -config CROS_EC_HOOK_TICK_INTERVAL - default 200000 - -endif # SOC_FAMILY_NPCX diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 deleted file mode 100644 index 3c59d5405e..0000000000 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 +++ /dev/null @@ -1,53 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# -# This file defines the correct defaults when using the NPCX7 series chipset -# - -if SOC_SERIES_NPCX7 - -# -# NPCX796FB: 1024 KiB Flash, 192 KiB code RAM, 62 KiB data RAM -# NPCX796FC: 512 KiB Flash, 192 KiB code RAM, 62 KiB data RAM -# NPCX797FC: 512 KiB Flash, 320 KiB code RAM, 62 KiB data RAM -# - -# Code RAM base for NPCX7 series -config CROS_EC_PROGRAM_MEMORY_BASE - default 0x10090000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC - default 0x10070000 if SOC_NPCX7M7FC - -config CROS_EC_RAM_BASE - default 0x200c0000 - -config CROS_EC_DATA_RAM_SIZE - default 0x00010000 - -config CROS_EC_RAM_SIZE - default 0x0000f800 - -config FLASH_SIZE - default 1024 if SOC_NPCX7M6FB - default 512 if SOC_NPCX7M6FC || SOC_NPCX7M7FC - -config CROS_EC_RO_MEM_OFF - default 0x0 - -# NPCX796FB/NPCX796FC: Image size limited by code RAM size (192 KiB) -# NPCX797FC: Image size limited by 1/2 Flash size (256 KiB) -config CROS_EC_RO_SIZE - default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC - default 0x40000 if SOC_NPCX7M7FC - -# RW firmware in program memory - Identical to RO, only one image loaded at a -# time. -config CROS_EC_RW_MEM_OFF - default 0x0 - -config CROS_EC_RW_SIZE - default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC - default 0x40000 if SOC_NPCX7M7FC - -endif # SOC_SERIES_NPCX7 diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 deleted file mode 100644 index 5fd1fbd308..0000000000 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 +++ /dev/null @@ -1,51 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# -# This file defines the correct defaults when using the NPCX9 series chipset -# - -if SOC_SERIES_NPCX9 - -# -# NPCX993F: 512 KiB Flash, 256 KiB code RAM, 64 KiB data RAM -# NPCX996F: 512 KiB Flash, 192 KiB code RAM, 64 KiB data RAM -# - -# Code RAM base for NPCX9 series -config CROS_EC_PROGRAM_MEMORY_BASE - default 0x10080000 if SOC_NPCX9M3F - default 0x10090000 if SOC_NPCX9M6F - -config CROS_EC_RAM_BASE - default 0x200c0000 - -config CROS_EC_DATA_RAM_SIZE - default 0x0000f800 - -config CROS_EC_RAM_SIZE - default 0x0000f800 - -config FLASH_SIZE - default 512 - -config CROS_EC_RO_MEM_OFF - default 0x0 - -# NPCX993F: Image size limited by 1/2 Flash size (256 KiB) and -# code RAM size (256 KiB) -# NPCX996F: Image size limited by code RAM size (192 KiB) - -config CROS_EC_RO_SIZE - default 0x40000 if SOC_NPCX9M3F - default 0x30000 if SOC_NPCX9M6F - -config CROS_EC_RW_MEM_OFF - default 0x0 - -config CROS_EC_RW_SIZE - default 0x40000 if SOC_NPCX9M3F - default 0x30000 if SOC_NPCX9M6F - -endif # SOC_SERIES_NPCX9 diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 deleted file mode 100644 index dab9e6b8b2..0000000000 --- a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if SOC_FAMILY_RISCV_ITE - -# Code RAM base for IT8XXX2 -config CROS_EC_PROGRAM_MEMORY_BASE - default 0x80000000 - -# The total RAM size of IT8xxx2 is 60 KB. -# The first 4KB block be always reserved for ram code functions, -# so the total available RAM size will be 56KB. -config CROS_EC_RAM_BASE - default 0x80101000 - -config CROS_EC_DATA_RAM_SIZE - default 0x0000e000 - -config CROS_EC_RAM_SIZE - default 0x0000e000 - -# The 512KB flash space layout are as the below: -# - RO image starts at the beginning of flash. -# - RW image starts at the second half of flash. -config CROS_EC_RO_MEM_OFF - default 0x0 - -config CROS_EC_RO_SIZE - default 0x40000 - -config CROS_EC_RW_MEM_OFF - default 0x40000 - -config CROS_EC_RW_SIZE - default 0x40000 - -config FLASH_LOAD_OFFSET - default CROS_EC_RW_MEM_OFF if CROS_EC_RW - -endif # SOC_FAMILY_RISCV_ITE |