diff options
Diffstat (limited to 'zephyr/app')
| -rw-r--r-- | zephyr/app/CMakeLists.txt | 5 | ||||
| -rw-r--r-- | zephyr/app/Kconfig | 5 | ||||
| -rw-r--r-- | zephyr/app/ec/CMakeLists.txt | 9 | ||||
| -rw-r--r-- | zephyr/app/ec/Kconfig | 137 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx | 53 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 | 53 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 | 51 | ||||
| -rw-r--r-- | zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 | 41 | ||||
| -rw-r--r-- | zephyr/app/ec/ec_app_main.c | 119 | ||||
| -rw-r--r-- | zephyr/app/ec/include/ec_app_main.h | 6 | ||||
| -rw-r--r-- | zephyr/app/ec/main_shim.c | 22 | ||||
| -rw-r--r-- | zephyr/app/ec/soc/Kconfig | 82 |
12 files changed, 0 insertions, 583 deletions
diff --git a/zephyr/app/CMakeLists.txt b/zephyr/app/CMakeLists.txt deleted file mode 100644 index dfc45f19f9..0000000000 --- a/zephyr/app/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -add_subdirectory_ifdef(CONFIG_CROS_EC ec) diff --git a/zephyr/app/Kconfig b/zephyr/app/Kconfig deleted file mode 100644 index 3cac46afa7..0000000000 --- a/zephyr/app/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -rsource "ec/Kconfig" diff --git a/zephyr/app/ec/CMakeLists.txt b/zephyr/app/ec/CMakeLists.txt deleted file mode 100644 index f12067a5b5..0000000000 --- a/zephyr/app/ec/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -zephyr_library_include_directories(include) -zephyr_library_sources(ec_app_main.c) -if(NOT DEFINED CONFIG_ZTEST) - zephyr_library_sources(main_shim.c) -endif() diff --git a/zephyr/app/ec/Kconfig b/zephyr/app/ec/Kconfig deleted file mode 100644 index 9f4bdd95a1..0000000000 --- a/zephyr/app/ec/Kconfig +++ /dev/null @@ -1,137 +0,0 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -menuconfig CROS_EC - bool "Chromium OS EC app" - imply SHELL - imply SHELL_MINIMAL - imply PRINTK - help - Enable the common Chromium OS EC application. This prints a message, - starts the EC tasks and sets up any drivers that are needed. - - This depends on PLATFORM_EC at present, since without the shimmed - tasks, almost nothing can operate. - -if CROS_EC - -rsource "soc/Kconfig" -orsource "chip/$(ARCH)/*/Kconfig.*" - -config LTO - bool "Link Time Optimization (LTO)" - default y if !SOC_POSIX - help - Enable the Link Time Optimization (LTO) feature for the toolchain. - LTO expands the scope of optimizations to encompass the whole program, - reducing the image size. - - At this time, LTO is only enabled for Chromium OS source files and - is not enabled for the Zephyr kernel or drivers due. - https://github.com/zephyrproject-rtos/zephyr/issues/2112 - -choice CBPRINTF_IMPLEMENTATION - default CBPRINTF_NANO - -endchoice - -choice - prompt "Chromium OS EC firmware section" - -config CROS_EC_RO - bool "This build is will be for the RO copy of the EC" - help - This build will be used to produce a copy for the read-only - section of the EC firmware. - -config CROS_EC_RW - bool "This build is will be for the RW copy of the EC" - help - This build will be used to produce a copy for the read-write - section of the EC firmware. - -endchoice - -config CROS_EC_ACTIVE_COPY - string - default "RO" if CROS_EC_RO - default "RW" if CROS_EC_RW - help - When the active copy name is output to a console, this - string will be displayed. - -config CROS_EC_HOOK_TICK_INTERVAL - int "The interval time for the HOOK_TICK" - default 250000 - help - Specificies the interval time for the HOOK_TICK, specified in - microseconds. Modules register with HOOK_TICK to be called - periodically by the HOOKS task. The interval must be shorter than - 1 second and is set according the EC chipset's sleep requirements. - -# When building for the host, we still need values for the various memory -# sizes, though they aren't actually used, so just set some reasonable-looking -# values and then ignore them. -config CROS_EC_RAM_SIZE - hex "The total available RAM size." - default 0x0000f800 if ARCH_POSIX - help - This value describes the total available RAM size for the chip. - -config CROS_EC_DATA_RAM_SIZE - hex "The total available RAM size for data." - default 0x00010000 if ARCH_POSIX - help - This value describes the total available RAM size for data on the chip. - -config CROS_EC_RAM_BASE - hex "Base address of RAM for the chip." - default 0x200c0000 if ARCH_POSIX - help - Base address of RAM for the chip. - -config CROS_EC_PROGRAM_MEMORY_BASE - hex "The base address of the program memory region." - default 0x10090000 if ARCH_POSIX - help - This will be used (among other things) to calculate the current PC's - offset within the program memory. - -config CROS_EC_RO_MEM_OFF - hex "The RO region's offset." - default 0x0 if ARCH_POSIX - help - This will be used to determine if the current PC is in the RO section. - -config CROS_EC_RO_SIZE - hex "The size of the RO region." - default 0xb000 if ARCH_POSIX - help - This will be used (along with SYSTEM_RO_MEM_OFF) to determine if the - current PC is in the RO section. - -config CROS_EC_RW_MEM_OFF - hex "The RW region's offset." - default 0xb000 if ARCH_POSIX - help - This will be used to determine if the current PC is in the RW section. - -config CROS_EC_RW_SIZE - hex "The size of the RW region." - default 0x75000 if ARCH_POSIX - help - This will be used (along with SYSTEM_RW_MEM_OFF) to determine if the - current PC is in the RW section. - -# By default, a unit test doesn't need shimmed tasks. -config SHIMMED_TASKS - bool "Add support for shimming in platform/ec tasks as Zephyr threads" - default n if ARCH_POSIX - help - When this option is enabled, a shimmed_tasks.h header with the - CROS_EC_TASK_LIST defined needs to be included for the project to - build. The CROS_EC_TASK_LIST defines a list of CROS_EC_TASK that - should be shimmed in. - -endif # CROS_EC diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx deleted file mode 100644 index 2da9252775..0000000000 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx +++ /dev/null @@ -1,53 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# -# This file defines the default config values shared by all NPCX chipsets -# - -if SOC_FAMILY_NPCX - -# Enable NPCX firmware header generator -config NPCX_HEADER - default y - -choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE - default NPCX_HEADER_SPI_MAX_CLOCK_50 -endchoice - -choice NPCX_HEADER_SPI_READ_MODE_CHOICE - default NPCX_HEADER_SPI_READ_MODE_DUAL -endchoice - -choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE - default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2 -endchoice - -# ADC -# The resolution and oversamplig values are fixed by the NPCX ADC driver -config PLATFORM_EC_ADC_RESOLUTION - default 10 - -config PLATFORM_EC_ADC_OVERSAMPLING - default 0 - -# Set the system clock to 15MHz. -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 15000000 - -if WATCHDOG - -# Set the delay time for printing panic data. -# 1 cycle is about 32ms. 500ms is about 16 cycles. -config WDT_NPCX_DELAY_CYCLES - default 16 - -endif # WATCHDOG - -# The maximum supported time the NPCX can spend in deep-sleep with instant -# wake is 200 ms, so the hook tick interval is set to match. -config CROS_EC_HOOK_TICK_INTERVAL - default 200000 - -endif # SOC_FAMILY_NPCX diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 deleted file mode 100644 index 3c59d5405e..0000000000 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 +++ /dev/null @@ -1,53 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# -# This file defines the correct defaults when using the NPCX7 series chipset -# - -if SOC_SERIES_NPCX7 - -# -# NPCX796FB: 1024 KiB Flash, 192 KiB code RAM, 62 KiB data RAM -# NPCX796FC: 512 KiB Flash, 192 KiB code RAM, 62 KiB data RAM -# NPCX797FC: 512 KiB Flash, 320 KiB code RAM, 62 KiB data RAM -# - -# Code RAM base for NPCX7 series -config CROS_EC_PROGRAM_MEMORY_BASE - default 0x10090000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC - default 0x10070000 if SOC_NPCX7M7FC - -config CROS_EC_RAM_BASE - default 0x200c0000 - -config CROS_EC_DATA_RAM_SIZE - default 0x00010000 - -config CROS_EC_RAM_SIZE - default 0x0000f800 - -config FLASH_SIZE - default 1024 if SOC_NPCX7M6FB - default 512 if SOC_NPCX7M6FC || SOC_NPCX7M7FC - -config CROS_EC_RO_MEM_OFF - default 0x0 - -# NPCX796FB/NPCX796FC: Image size limited by code RAM size (192 KiB) -# NPCX797FC: Image size limited by 1/2 Flash size (256 KiB) -config CROS_EC_RO_SIZE - default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC - default 0x40000 if SOC_NPCX7M7FC - -# RW firmware in program memory - Identical to RO, only one image loaded at a -# time. -config CROS_EC_RW_MEM_OFF - default 0x0 - -config CROS_EC_RW_SIZE - default 0x30000 if SOC_NPCX7M6FB || SOC_NPCX7M6FC - default 0x40000 if SOC_NPCX7M7FC - -endif # SOC_SERIES_NPCX7 diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 deleted file mode 100644 index 5fd1fbd308..0000000000 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 +++ /dev/null @@ -1,51 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# -# This file defines the correct defaults when using the NPCX9 series chipset -# - -if SOC_SERIES_NPCX9 - -# -# NPCX993F: 512 KiB Flash, 256 KiB code RAM, 64 KiB data RAM -# NPCX996F: 512 KiB Flash, 192 KiB code RAM, 64 KiB data RAM -# - -# Code RAM base for NPCX9 series -config CROS_EC_PROGRAM_MEMORY_BASE - default 0x10080000 if SOC_NPCX9M3F - default 0x10090000 if SOC_NPCX9M6F - -config CROS_EC_RAM_BASE - default 0x200c0000 - -config CROS_EC_DATA_RAM_SIZE - default 0x0000f800 - -config CROS_EC_RAM_SIZE - default 0x0000f800 - -config FLASH_SIZE - default 512 - -config CROS_EC_RO_MEM_OFF - default 0x0 - -# NPCX993F: Image size limited by 1/2 Flash size (256 KiB) and -# code RAM size (256 KiB) -# NPCX996F: Image size limited by code RAM size (192 KiB) - -config CROS_EC_RO_SIZE - default 0x40000 if SOC_NPCX9M3F - default 0x30000 if SOC_NPCX9M6F - -config CROS_EC_RW_MEM_OFF - default 0x0 - -config CROS_EC_RW_SIZE - default 0x40000 if SOC_NPCX9M3F - default 0x30000 if SOC_NPCX9M6F - -endif # SOC_SERIES_NPCX9 diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 deleted file mode 100644 index dab9e6b8b2..0000000000 --- a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if SOC_FAMILY_RISCV_ITE - -# Code RAM base for IT8XXX2 -config CROS_EC_PROGRAM_MEMORY_BASE - default 0x80000000 - -# The total RAM size of IT8xxx2 is 60 KB. -# The first 4KB block be always reserved for ram code functions, -# so the total available RAM size will be 56KB. -config CROS_EC_RAM_BASE - default 0x80101000 - -config CROS_EC_DATA_RAM_SIZE - default 0x0000e000 - -config CROS_EC_RAM_SIZE - default 0x0000e000 - -# The 512KB flash space layout are as the below: -# - RO image starts at the beginning of flash. -# - RW image starts at the second half of flash. -config CROS_EC_RO_MEM_OFF - default 0x0 - -config CROS_EC_RO_SIZE - default 0x40000 - -config CROS_EC_RW_MEM_OFF - default 0x40000 - -config CROS_EC_RW_SIZE - default 0x40000 - -config FLASH_LOAD_OFFSET - default CROS_EC_RW_MEM_OFF if CROS_EC_RW - -endif # SOC_FAMILY_RISCV_ITE diff --git a/zephyr/app/ec/ec_app_main.c b/zephyr/app/ec/ec_app_main.c deleted file mode 100644 index 7cc5b170f1..0000000000 --- a/zephyr/app/ec/ec_app_main.c +++ /dev/null @@ -1,119 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <kernel.h> -#include <sys/printk.h> -#include <shell/shell_uart.h> -#include <zephyr.h> - -#include "button.h" -#include "chipset.h" -#include "ec_tasks.h" -#include "hooks.h" -#include "keyboard_scan.h" -#include "lpc.h" -#include "system.h" -#include "vboot.h" -#include "watchdog.h" -#include "zephyr_espi_shim.h" -#include "ec_app_main.h" - -/* For testing purposes this is not named main. See main_shim.c for the real - * main() function. - */ -void ec_app_main(void) -{ - system_common_pre_init(); - - /* - * Initialize reset logs. This needs to be done before any updates of - * reset logs because we need to verify if the values remain the same - * after every EC reset. - */ - if (IS_ENABLED(CONFIG_CMD_AP_RESET_LOG)) { - init_reset_log(); - } - - system_print_banner(); - - if (IS_ENABLED(CONFIG_PLATFORM_EC_WATCHDOG)) { - watchdog_init(); - } - - /* - * Keyboard scan init/Button init can set recovery events to - * indicate to host entry into recovery mode. Before this is - * done, LPC_HOST_EVENT_ALWAYS_REPORT mask needs to be initialized - * correctly. - */ - if (IS_ENABLED(CONFIG_HOSTCMD_X86)) { - lpc_init_mask(); - } - - if (IS_ENABLED(HAS_TASK_KEYSCAN)) { - keyboard_scan_init(); - } - - if (IS_ENABLED(CONFIG_DEDICATED_RECOVERY_BUTTON) || - IS_ENABLED(CONFIG_VOLUME_BUTTONS)) { - button_init(); - } - - if (IS_ENABLED(CONFIG_PLATFORM_EC_ESPI)) { - if (zephyr_shim_setup_espi() < 0) { - printk("Failed to init eSPI!\n"); - } - } - - if (IS_ENABLED(CONFIG_PLATFORM_EC_VBOOT_EFS2)) { - /* - * For RO, it behaves as follows: - * In recovery, it enables PD communication and returns. - * In normal boot, it verifies and jumps to RW. - * For RW, it returns immediately. - */ - vboot_main(); - } - - /* - * Hooks run from the system workqueue and must be the lowest priority - * thread. By default, the system workqueue is run at the lowest - * cooperative thread priority, blocking all preemptive threads until - * the deferred work is completed. - */ - k_thread_priority_set(&k_sys_work_q.thread, LOWEST_THREAD_PRIORITY); - - /* Call init hooks before main tasks start */ - if (IS_ENABLED(CONFIG_PLATFORM_EC_HOOKS)) { - hook_notify(HOOK_INIT); - } - - - /* - * Increase priority of shell thread. - * This is temporary code that'll be removed - * after the feature outlined in bug b/191795553 - * is implemented. - */ - { - static const struct shell *shell; - - shell = shell_backend_uart_get_ptr(); - k_thread_priority_set(shell->ctx->tid, - K_HIGHEST_APPLICATION_THREAD_PRIO); - } - - /* - * Print the init time. Not completely accurate because it can't take - * into account the time before timer_init(), but it'll at least catch - * the majority of the time. - */ - cprints(CC_SYSTEM, "Inits done"); - - /* Start the EC tasks after performing all main initialization */ - if (IS_ENABLED(CONFIG_SHIMMED_TASKS)) { - start_ec_tasks(); - } -} diff --git a/zephyr/app/ec/include/ec_app_main.h b/zephyr/app/ec/include/ec_app_main.h deleted file mode 100644 index a5043be84a..0000000000 --- a/zephyr/app/ec/include/ec_app_main.h +++ /dev/null @@ -1,6 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -void ec_app_main(void); diff --git a/zephyr/app/ec/main_shim.c b/zephyr/app/ec/main_shim.c deleted file mode 100644 index 35f45e0286..0000000000 --- a/zephyr/app/ec/main_shim.c +++ /dev/null @@ -1,22 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <kernel.h> -#include "ec_app_main.h" - -/** A stub main to call the real ec app main function. LCOV_EXCL_START */ -void main(void) -{ - ec_app_main(); - -#ifdef CONFIG_THREAD_MONITOR - /* - * Avoid returning so that the main stack is displayed by the - * "kernel stacks" shell command. - */ - k_sleep(K_FOREVER); -#endif -} -/* LCOV_EXCL_STOP */ diff --git a/zephyr/app/ec/soc/Kconfig b/zephyr/app/ec/soc/Kconfig deleted file mode 100644 index d7befb39b7..0000000000 --- a/zephyr/app/ec/soc/Kconfig +++ /dev/null @@ -1,82 +0,0 @@ -menuconfig AP - bool "Enable AP SoC support code" - default y - help - This device has an application processor (AP) on-board and - support code should be enabled. - -if AP - -choice - prompt "SoC chipset generation" - -config AP_X86_INTEL_CML - bool "AP is CML chipset" - select AP_X86_INTEL - help - The application processor is Intel Comet Lake (CML) chipset. - -config AP_X86_INTEL_TGL - bool "AP is TGL chipset" - select AP_X86_INTEL - help - The application processor is Intel Tiger Lake (TGL) chipset. - -config AP_X86_INTEL_ADL - bool "AP is ADL chipset" - select AP_X86_INTEL - help - The application processor is Intel Alder Lake (ADL) chipset. - -config AP_X86_AMD - bool "AP is an AMD chipset" - select AP_x86 - help - The application processor is a product of AMD. - -config AP_ARM_MTK_MT8192 - bool "MediaTek MT8192" - select AP_AARCH64 - help - The application processor is a MediaTek MT8192 processor. - -config AP_ARM_QUALCOMM_SC7180 - bool "Qualcomm Snapdragon SC7180" - select AP_AARCH64 - help - The application processor is a Qualcomm Snapdragon SC7180 - ARMv8 processor. - -config AP_ARM_QUALCOMM_SC7280 - bool "Qualcomm Snapdragon SC7280" - select AP_AARCH64 - help - The application processor is a Qualcomm Snapdragon SC7280 - ARMv8 processor. - -endchoice - -# Invisible meta-symbols generated by the selected chipset. -config AP_X86_INTEL - bool - select AP_X86 - help - The application processor (AP) is an Intel SoC. - -config AP_X86 - bool - help - The application processor (AP) is X86-like. - -config AP_AARCH64 - bool - select AP_ARM - help - The application processor (AP) is 64-bit ARMv8 architecture. - -config AP_ARM - bool - help - The application processor (AP) is ARM-like. - -endif # AP |