diff options
Diffstat (limited to 'zephyr/boards/arm/npcx_evb')
-rw-r--r-- | zephyr/boards/arm/npcx_evb/Kconfig.board | 18 | ||||
-rw-r--r-- | zephyr/boards/arm/npcx_evb/Kconfig.defconfig | 7 | ||||
-rw-r--r-- | zephyr/boards/arm/npcx_evb/npcx7_evb.dts | 22 | ||||
-rw-r--r-- | zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig | 55 | ||||
-rw-r--r-- | zephyr/boards/arm/npcx_evb/npcx9_evb.dts | 21 | ||||
-rw-r--r-- | zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig | 54 | ||||
-rw-r--r-- | zephyr/boards/arm/npcx_evb/npcx_evb.dtsi | 169 |
7 files changed, 0 insertions, 346 deletions
diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.board b/zephyr/boards/arm/npcx_evb/Kconfig.board deleted file mode 100644 index 0ac4a80833..0000000000 --- a/zephyr/boards/arm/npcx_evb/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Note: this Zephyr board more closely represents the Chrome OS -# concept of a baseboard. Zephyr boards and Chrome OS boards do not -# have a 1:1 mapping. -config BOARD_NPCX7_EVB - bool "NPCX7 Evaluation Board" - depends on SOC_NPCX7M6FB || SOC_NPCX7M6FC || SOC_NPCX7M7FC - # Allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT - -config BOARD_NPCX9_EVB - bool "NPCX9 Evaluation Board" - depends on SOC_NPCX9M3F || SOC_NPCX9M6F - # Allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig deleted file mode 100644 index c0c874ad26..0000000000 --- a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -config BOARD - default "npcx7_evb" if BOARD_NPCX7_EVB - default "npcx9_evb" if BOARD_NPCX9_EVB diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts deleted file mode 100644 index c20589d637..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx7.dtsi> - -/* - * #include <nuvoton/npcx7m6fb.dtsi> - * #include <nuvoton/npcx7m6fc.dtsi> - * #include <nuvoton/npcx7m7fc.dtsi> - */ -#include <nuvoton/npcx7m6fc.dtsi> -#include "npcx_evb.dtsi" - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */ -}; diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig deleted file mode 100644 index b2fc879cbc..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX7=y -# NPCX7 soc list -# CONFIG_SOC_NPCX7M6FB -# CONFIG_SOC_NPCX7M6FC -# CONFIG_SOC_NPCX7M7FC -CONFIG_SOC_NPCX7M6FC=y - -# Platform Configuration -CONFIG_BOARD_NPCX7_EVB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# I2C -CONFIG_I2C=y - -# ADC -CONFIG_ADC=y -CONFIG_ADC_SHELL=n - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts deleted file mode 100644 index 4ab68cdde1..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx9.dtsi> - -/* - * #include <nuvoton/npcx9m3f.dtsi> - * #include <nuvoton/npcx9m6f.dtsi> - */ -#include <nuvoton/npcx9m6f.dtsi> -#include "npcx_evb.dtsi" - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>; -}; diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig deleted file mode 100644 index 9a946584ef..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX9=y -# NPCX9 soc list -# CONFIG_SOC_NPCX9M3F -# CONFIG_SOC_NPCX9M6F -CONFIG_SOC_NPCX9M6F=y - -# Platform Configuration -CONFIG_BOARD_NPCX9_EVB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# I2C -CONFIG_I2C=y - -# ADC -CONFIG_ADC=y -CONFIG_ADC_SHELL=n - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi deleted file mode 100644 index 61a1e79783..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <dt-bindings/gpio_defines.h> - -/ { - model = "Nuvoton NPCX Evaluation Board"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - cros,rtc = &mtc; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_evb_0_0 { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_EVB_0"; - label = "I2C0_0"; - }; - i2c_evb_1_0 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_EVB_1"; - label = "I2C1_0"; - }; - i2c_evb_2_0 { - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_EVB_2"; - label = "I2C2_0"; - }; - i2c_evb_3_0 { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_EVB_3"; - label = "I2C3_0"; - }; - i2c_evb_7_0 { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_EVB_7"; - label = "I2C7_0"; - }; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_ch_0 { - label = "ADC0"; - enum-name = "ADC_EVB_CH_0"; - channel = <0>; - }; - adc_ch_1 { - label = "ADC1"; - enum-name = "ADC_EVB_CH_1"; - channel = <1>; - }; - adc_ch_2 { - label = "ADC2"; - enum-name = "ADC_EVB_CH_2"; - channel = <2>; - }; - adc_ch_3 { - label = "ADC3"; - enum-name = "ADC_EVB_CH_3"; - channel = <3>; - }; - adc_ch_4 { - label = "ADC4"; - enum-name = "ADC_EVB_CH_4"; - channel = <4>; - }; - }; - - vsby-psl-in-list { - /* Use PSL_IN1/2/3 as detection pins from hibernate mode */ - psl-in-pads = <&psl_in1 &psl_in2 &psl_in3>; - }; -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl7 { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -/* Power switch logic input pads */ -&psl_in1 { - flag = <NPCX_PSL_FALLING_EDGE>; -}; -&psl_in2 { - flag = <NPCX_PSL_FALLING_EDGE>; -}; -&psl_in3 { - flag = <NPCX_PSL_RISING_EDGE>; -}; - -&cros_kb_raw { - status = "okay"; - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso02_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - >; -}; |