diff options
Diffstat (limited to 'zephyr/boards/arm')
37 files changed, 0 insertions, 2304 deletions
diff --git a/zephyr/boards/arm/brya/Kconfig.board b/zephyr/boards/arm/brya/Kconfig.board deleted file mode 100644 index 8add483941..0000000000 --- a/zephyr/boards/arm/brya/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# "BOARD" below refers to a Zephyr board, which does not have a 1:1 -# mapping with the Chrome OS concept of a board. By Zephyr's -# conventions, we'll still call it "BOARD_*" to make this more -# applicable to be upstreamed, even though this code is shared by all -# projects using Brya baseboard. -config BOARD_BRYA - bool "Google Brya Baseboard" - depends on SOC_NPCX9M3F - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/brya/Kconfig.defconfig b/zephyr/boards/arm/brya/Kconfig.defconfig deleted file mode 100644 index e4de179311..0000000000 --- a/zephyr/boards/arm/brya/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_BRYA - -config BOARD - default "brya" - -endif # BOARD_BRYA diff --git a/zephyr/boards/arm/brya/board.cmake b/zephyr/boards/arm/brya/board.cmake deleted file mode 100644 index 67ade59f57..0000000000 --- a/zephyr/boards/arm/brya/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin) - diff --git a/zephyr/boards/arm/brya/brya.dts b/zephyr/boards/arm/brya/brya.dts deleted file mode 100644 index 4ba8704cd2..0000000000 --- a/zephyr/boards/arm/brya/brya.dts +++ /dev/null @@ -1,188 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx9.dtsi> -#include <dt-bindings/gpio_defines.h> -#include <nuvoton/npcx9m3f.dtsi> - -/ { - model = "Google Brya Baseboard"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - i2c_sensor: sensor { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_SENSOR"; - label = "SENSOR"; - }; - tcpc0_2 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_USB_C0_C2_TCPC"; - label = "TCPC0,2"; - }; - tcpc1 { - i2c-port = <&i2c4_1>; - enum-name = "I2C_PORT_USB_C1_TCPC"; - label = "TCPC1"; - }; - ppc0_2 { - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_USB_C0_C2_PPC"; - label = "PPC0,2"; - }; - ppc1 { - i2c-port = <&i2c6_1>; - enum-name = "I2C_PORT_USB_C1_PPC"; - label = "PPC1"; - }; - retimer0_2 { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_USB_C0_C2_MUX"; - label = "RETIMER0,2"; - }; - battery { - i2c-port = <&i2c5_0>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - eeprom { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_EEPROM"; - label = "EEPROM"; - }; - charger { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_CHARGER"; - label = "EEPROM"; - }; - }; - - named-pwms { - compatible = "named-pwms"; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>; -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c4_1 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl4 { - status = "okay"; -}; - -&i2c5_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c6_1 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl6 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl7 { - status = "okay"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - &alt9_no_kso13_sl - &alt9_no_kso14_sl - >; -}; diff --git a/zephyr/boards/arm/brya/brya_defconfig b/zephyr/boards/arm/brya/brya_defconfig deleted file mode 100644 index e8c412a592..0000000000 --- a/zephyr/boards/arm/brya/brya_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX9=y - -# Platform Configuration -CONFIG_SOC_NPCX9M3F=y -CONFIG_BOARD_BRYA=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/herobrine_npcx9/Kconfig.board b/zephyr/boards/arm/herobrine_npcx9/Kconfig.board deleted file mode 100644 index d9e7faf3af..0000000000 --- a/zephyr/boards/arm/herobrine_npcx9/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# "BOARD" below refers to a Zephyr board, which does not have a 1:1 -# mapping with the Chrome OS concept of a board. By Zephyr's -# conventions, we'll still call it "BOARD_*" to make this more -# applicable to be upstreamed, even though this code is shared by all -# projects using Herobrine-NPCX9 baseboard. -config BOARD_HEROBRINE_NPCX9 - bool "Google Herobrine-NPCX9 Baseboard" - depends on SOC_NPCX9M3F - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig b/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig deleted file mode 100644 index 65f3225d91..0000000000 --- a/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_HEROBRINE_NPCX9 - -config BOARD - default "herobrine_npcx9" - -endif # BOARD_HEROBRINE_NPCX9 diff --git a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts deleted file mode 100644 index 34884a8275..0000000000 --- a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx9.dtsi> -#include <dt-bindings/adc/adc.h> -#include <dt-bindings/gpio_defines.h> -#include <dt-bindings/wake_mask_event_defines.h> -#include <nuvoton/npcx9m3f.dtsi> - -/ { - model = "Google Herobrine-NPCX9 Baseboard"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - cros,rtc = &pcf85063a; - }; - - ec-console { - compatible = "ec-console"; - - disabled = "hostcmd"; - }; - - ec-mkbp-host-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <(HOST_EVENT_LID_OPEN | \ - HOST_EVENT_POWER_BUTTON | \ - HOST_EVENT_AC_CONNECTED | \ - HOST_EVENT_AC_DISCONNECTED | \ - HOST_EVENT_HANG_DETECT | \ - HOST_EVENT_RTC | \ - HOST_EVENT_MODE_CHANGE | \ - HOST_EVENT_DEVICE)>; - }; - - ec-mkbp-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | \ - MKBP_EVENT_HOST_EVENT | \ - MKBP_EVENT_SENSOR_FIFO)>; - }; - - named-pwms { - compatible = "named-pwms"; - - kblight { - pwms = <&pwm3 0 0>; - label = "KBLIGHT"; - frequency = <10000>; - }; - displight { - pwms = <&pwm5 0 0>; - label = "DISPLIGHT"; - frequency = <4800>; - }; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - vbus { - label = "ADC_VBUS"; - enum-name = "ADC_VBUS"; - channel = <1>; - /* Measure VBUS through a 1/10 voltage divider */ - mul = <10>; - }; - amon_bmon { - label = "ADC_AMON_BMON"; - enum-name = "ADC_AMON_BMON"; - channel = <2>; - /* - * Adapter current output or battery charging/ - * discharging current (uV) 18x amplification on - * charger side. - */ - mul = <1000>; - div = <18>; - }; - psys { - label = "ADC_PSYS"; - enum-name = "ADC_PSYS"; - channel = <3>; - /* - * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, - * to read 0.8V @ 99 W, i.e. 124000 uW/mV. - */ - mul = <124000>; - }; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>; -}; - -/* Keyboard backlight */ -&pwm3 { - status = "okay"; -}; - -/* Display backlight */ -&pwm5 { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - >; -}; diff --git a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig deleted file mode 100644 index 907ae9ed34..0000000000 --- a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX9=y -CONFIG_SOC_NPCX9M3F=y - -# Platform Configuration -CONFIG_BOARD_HEROBRINE_NPCX9=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/kohaku/Kconfig.board b/zephyr/boards/arm/kohaku/Kconfig.board deleted file mode 100644 index c1a1718847..0000000000 --- a/zephyr/boards/arm/kohaku/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -config BOARD_KOHAKU - bool "Google Kohaku EC" - depends on SOC_NPCX7M6FC - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/kohaku/Kconfig.defconfig b/zephyr/boards/arm/kohaku/Kconfig.defconfig deleted file mode 100644 index 83b97d8ef7..0000000000 --- a/zephyr/boards/arm/kohaku/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_KOHAKU - -config BOARD - default "kohaku" - -endif # BOARD_KOHAKU diff --git a/zephyr/boards/arm/kohaku/board.cmake b/zephyr/boards/arm/kohaku/board.cmake deleted file mode 100644 index a204305534..0000000000 --- a/zephyr/boards/arm/kohaku/board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin) diff --git a/zephyr/boards/arm/kohaku/kohaku.dts b/zephyr/boards/arm/kohaku/kohaku.dts deleted file mode 100644 index 00e340faea..0000000000 --- a/zephyr/boards/arm/kohaku/kohaku.dts +++ /dev/null @@ -1,418 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx7.dtsi> -#include <dt-bindings/gpio_defines.h> -#include <nuvoton/npcx7m6fc.dtsi> - -/ { - model = "Google Kohaku EC"; - - aliases { - i2c-0 = &i2c0_0; - i2c-1 = &i2c1_0; - i2c-2 = &i2c2_0; - i2c-3 = &i2c3_0; - i2c-5 = &i2c5_0; - i2c-7 = &i2c7_0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - }; - - named-gpios { - compatible = "named-gpios"; - - lid_open { - gpios = <&gpiod 2 GPIO_INPUT>; - enum-name = "GPIO_LID_OPEN"; - label = "LID_OPEN"; - }; - wp_l { - gpios = <&gpioa 1 GPIO_INPUT>; - enum-name = "GPIO_WP_L"; - label = "WP_L"; - }; - power_button_l { - gpios = <&gpio0 1 GPIO_INPUT>; - enum-name = "GPIO_POWER_BUTTON_L"; - label = "POWER_BUTTON_L"; - }; - acok_od { - gpios = <&gpio0 0 GPIO_INPUT>; - enum-name = "GPIO_AC_PRESENT"; - label = "ACOK_OD"; - }; - slp_s0_l { - gpios = <&gpiod 5 GPIO_INPUT>; - enum-name = "GPIO_PCH_SLP_S0_L"; - label = "SLP_S0_L"; - }; - slp_s3_l { - gpios = <&gpioa 5 GPIO_INPUT>; - enum-name = "GPIO_PCH_SLP_S3_L"; - label = "SLP_S3_L"; - }; - slp_s4_l { - gpios = <&gpiod 4 GPIO_INPUT>; - enum-name = "GPIO_PCH_SLP_S4_L"; - label = "SLP_S4_L"; - }; - pg_ec_rsmrst_l { - gpios = <&gpioe 2 GPIO_INPUT>; - enum-name = "GPIO_RSMRST_L_PGOOD"; - label = "PG_EC_RSMRST_L"; - }; - pg_ec_all_sys_pwrgd { - gpios = <&gpiof 4 GPIO_INPUT>; - enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD"; - label = "PG_EC_ALL_SYS_PWRGD"; - }; - pp5000_a_pg_od { - gpios = <&gpiod 7 GPIO_INPUT>; - enum-name = "GPIO_PP5000_A_PG_OD"; - label = "PP5000_A_PG_OD"; - }; - base_sixaxis_int_l { - gpios = <&gpio5 6 GPIO_INPUT>; - label = "BASE_SIXAXIS_INT_L"; - }; - wfcam_vsync { - gpios = <&gpiob 7 GPIO_INPUT>; - label = "WFCAM_VSYNC"; - }; - tcs3400_int_odl { - gpios = <&gpio7 2 GPIO_INPUT>; - label = "TCS3400_INT_ODL"; - }; - usb_c0_ppc_int_odl { - gpios = <&gpioe 0 GPIO_INPUT>; - label = "USB_C0_PPC_INT_ODL"; - }; - usb_c1_ppc_int_odl { - gpios = <&gpioa 2 GPIO_INPUT>; - label = "USB_C1_PPC_INT_ODL"; - }; - usb_c0_tcpc_int_odl { - gpios = <&gpio6 2 GPIO_INPUT>; - label = "USB_C0_TCPC_INT_ODL"; - }; - usb_c1_tcpc_int_odl { - gpios = <&gpiof 5 GPIO_INPUT>; - label = "USB_C1_TCPC_INT_ODL"; - }; - usb_c0_bc12_int_odl { - gpios = <&gpio9 5 GPIO_INPUT>; - label = "USB_C0_BC12_INT_ODL"; - }; - usb_c1_bc12_int_odl { - gpios = <&gpioe 4 GPIO_INPUT>; - label = "USB_C1_BC12_INT_ODL"; - }; - ec_voldn_btn_odl { - gpios = <&gpio9 3 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "EC_VOLDN_BTN_ODL"; - }; - ec_volup_btn_odl { - gpios = <&gpio7 5 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "EC_VOLUP_BTN_ODL"; - }; - sys_reset_l { - gpios = <&gpioc 5 GPIO_ODR_HIGH>; - enum-name = "GPIO_SYS_RESET_L"; - label = "SYS_RESET_L"; - }; - entering_rw { - gpios = <&gpioe 3 GPIO_OUT_LOW>; - enum-name = "GPIO_ENTERING_RW"; - label = "ENTERING_RW"; - }; - pch_wake_l { - gpios = <&gpio7 4 GPIO_ODR_HIGH>; - enum-name = "GPIO_EC_PCH_WAKE_ODL"; - label = "PCH_WAKE_L"; - }; - pch_pwrbtn_l { - gpios = <&gpioc 1 GPIO_ODR_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - label = "PCH_PWRBTN_L"; - }; - en_pp5000_a { - gpios = <&gpioa 4 GPIO_OUT_LOW>; - enum-name = "GPIO_EN_PP5000_A"; - label = "EN_PP5000_A"; - }; - en_pp5000 { - gpios = <&gpioa 4 GPIO_OUT_LOW>; - enum-name = "GPIO_EN_PP5000"; - label = "EN_PP5000"; - }; - gpio_edp_bklten_od { - gpios = <&gpiod 3 GPIO_ODR_HIGH>; - enum-name = "GPIO_ENABLE_BACKLIGHT"; - label = "EDP_BKLTEN_OD"; - }; - en_a_rails { - gpios = <&gpioa 3 GPIO_OUT_LOW>; - enum-name = "GPIO_EN_A_RAILS"; - label = "EN_A_RAILS"; - }; - ec_pch_rsmrst_l { - gpios = <&gpioa 6 GPIO_OUT_LOW>; - enum-name = "GPIO_PCH_RSMRST_L"; - label = "EC_PCH_RSMRST_L"; - }; - ec_prochot_odl { - gpios = <&gpio6 3 GPIO_ODR_HIGH>; - enum-name = "GPIO_CPU_PROCHOT"; - label = "EC_PROCHOT_ODL"; - }; - ec_prochot_in_od { - gpios = <&gpio3 4 GPIO_INPUT>; - label = "EC_PROCHOT_IN_OD"; - }; - ec_pch_sys_pwrok { - gpios = <&gpio3 7 GPIO_OUT_LOW>; - enum-name = "GPIO_PCH_SYS_PWROK"; - label = "EC_PCH_SYS_PWROK"; - }; - cpu_c10_gate_l { - gpios = <&gpio6 7 GPIO_INPUT>; - label = "CPU_C10_GATE_L"; - }; - ec_int_l { - gpios = <&gpio7 0 GPIO_ODR_HIGH>; - label = "EC_INT_L"; - }; - ec_rst_odl { - gpios = <&gpio0 2 GPIO_INPUT>; - label = "EC_RST_ODL"; - }; - usb_c_oc_odl { - gpios = <&gpiob 1 GPIO_ODR_HIGH>; - label = "USB_C_OC_ODL"; - }; - usb_c0_tcpc_rst_odl { - gpios = <&gpio9 7 GPIO_ODR_HIGH>; - label = "USB_C0_TCPC_RST_ODL"; - }; - usb_c1_tcpc_rst_odl { - gpios = <&gpio3 2 GPIO_ODR_HIGH>; - label = "USB_C1_TCPC_RST_ODL"; - }; - usb_c0_bc12_chg_det_l { - gpios = <&gpio6 0 GPIO_INPUT>; - label = "USB_C0_BC12_CHG_DET_L"; - }; - usb_c1_bc12_chg_det_l { - gpios = <&gpio9 6 GPIO_INPUT>; - label = "USB_C1_BC12_CHG_DET_L"; - }; - usb_c0_bc12_vbus_on { - gpios = <&gpio9 4 GPIO_OUT_LOW>; - label = "USB_C0_BC12_VBUS_ON"; - }; - usb_c1_bc12_vbus_on { - gpios = <&gpioc 6 GPIO_OUT_LOW>; - label = "USB_C1_BC12_VBUS_ON"; - }; - ec_batt_pres_odl { - gpios = <&gpioe 1 GPIO_INPUT>; - label = "EC_BATT_PRES_ODL"; - }; - led_1_l { - gpios = <&gpioc 4 GPIO_OUT_HIGH>; - label = "LED_1_L"; - }; - led_2_l { - gpios = <&gpioc 3 GPIO_OUT_HIGH>; - label = "LED_2_L"; - }; - led_3_l { - gpios = <&gpioc 2 GPIO_OUT_HIGH>; - label = "LED_3_L"; - }; - ec_kb_bl_en { - gpios = <&gpio8 6 GPIO_OUT_LOW>; - label = "EC_KB_BL_EN"; - }; - edp_bklten_od { - gpios = <&gpiod 3 GPIO_ODR_HIGH>; - label = "EDP_BKLTEN_OD"; - }; - lid_accel_int_l { - gpios = <&gpio5 0 GPIO_INPUT>; - label = "LID_ACCEL_INT_L"; - }; - m2_sd_pln { - gpios = <&gpioa 0 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "M2_SD_PLN"; - }; - imvp8_pe { - gpios = <&gpioa 7 GPIO_INPUT>; - label = "IMVP8_PE"; - }; - i2c0_scl { - gpios = <&gpiob 5 GPIO_INPUT>; - label = "I2C0_SCL"; - }; - i2c0_sda { - gpios = <&gpiob 4 GPIO_INPUT>; - label = "I2C0_SDA"; - }; - i2c1_scl { - gpios = <&gpio9 0 GPIO_INPUT>; - label = "I2C1_SCL"; - }; - i2c1_sda { - gpios = <&gpio8 7 GPIO_INPUT>; - label = "I2C1_SDA"; - }; - i2c2_scl { - gpios = <&gpio9 2 GPIO_INPUT>; - label = "I2C2_SCL"; - }; - i2c2_sda { - gpios = <&gpio9 1 GPIO_INPUT>; - label = "I2C2_SDA"; - }; - i2c3_scl { - gpios = <&gpiod 1 GPIO_INPUT>; - label = "I2C3_SCL"; - }; - i2c3_sda { - gpios = <&gpiod 0 GPIO_INPUT>; - label = "I2C3_SDA"; - }; - i2c5_scl { - gpios = <&gpio3 3 GPIO_INPUT>; - label = "I2C5_SCL"; - }; - i2c5_sda { - gpios = <&gpio3 6 GPIO_INPUT>; - label = "I2C5_SDA"; - }; - i2c7_scl { - gpios = <&gpiob 3 GPIO_INPUT>; - label = "I2C7_SCL"; - }; - i2c7_sda { - gpios = <&gpiob 2 GPIO_INPUT>; - label = "I2C7_SDA"; - }; - tp58 { - gpios = <&gpio0 4 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP58"; - }; - tp73 { - gpios = <&gpio8 2 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP73"; - }; - tp18 { - gpios = <&gpioc 0 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP18"; - }; - tp54 { - gpios = <&gpio4 0 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP54"; - }; - tp56 { - gpios = <&gpio6 1 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP56"; - }; - tp57 { - gpios = <&gpio8 1 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP57"; - }; - tp55 { - gpios = <&gpio7 3 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP55"; - }; - tp59 { - gpios = <&gpiob 0 (GPIO_INPUT | GPIO_PULL_UP)>; - label = "TP59"; - }; - kbd_kso2 { - gpios = <&gpio1 7 GPIO_OUT_LOW>; - label = "KBD_KSO2"; - }; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - lvol-io-pads = <&lvol_iob4 &lvol_iob5 /* I2C_SDA0 & SCL0 */ - &lvol_io50>; /* GPIO50 */ - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */ -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c5_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl7 { - status = "okay"; -}; diff --git a/zephyr/boards/arm/kohaku/kohaku.yaml b/zephyr/boards/arm/kohaku/kohaku.yaml deleted file mode 100644 index 48cc85e7df..0000000000 --- a/zephyr/boards/arm/kohaku/kohaku.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2020 Google LLC. -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: kohaku -name: "Google Kohaku (Samsung Galaxy Chromebook) Embedded Controller" -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -ram: 64 -flash: 512 -testing: - ignore_tags: - - net - - bluetooth diff --git a/zephyr/boards/arm/kohaku/kohaku_defconfig b/zephyr/boards/arm/kohaku/kohaku_defconfig deleted file mode 100644 index eccf6da6ab..0000000000 --- a/zephyr/boards/arm/kohaku/kohaku_defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX7=y -CONFIG_SOC_NPCX7M6FC=y - -# Platform Configuration -CONFIG_BOARD_KOHAKU=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx9/Kconfig.board b/zephyr/boards/arm/npcx9/Kconfig.board deleted file mode 100644 index e4b184d83e..0000000000 --- a/zephyr/boards/arm/npcx9/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -config BOARD_NPCX9 - bool "NPCX9 Zephyr Board" - depends on SOC_NPCX9M3F - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/npcx9/Kconfig.defconfig b/zephyr/boards/arm/npcx9/Kconfig.defconfig deleted file mode 100644 index 9b83915f04..0000000000 --- a/zephyr/boards/arm/npcx9/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_NPCX9 - -config BOARD - default "npcx9" - -endif # BOARD_TROGDOR diff --git a/zephyr/boards/arm/npcx9/board.cmake b/zephyr/boards/arm/npcx9/board.cmake deleted file mode 100644 index a204305534..0000000000 --- a/zephyr/boards/arm/npcx9/board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin) diff --git a/zephyr/boards/arm/npcx9/npcx9.dts b/zephyr/boards/arm/npcx9/npcx9.dts deleted file mode 100644 index ab44d8119e..0000000000 --- a/zephyr/boards/arm/npcx9/npcx9.dts +++ /dev/null @@ -1,199 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx9.dtsi> -#include <dt-bindings/adc/adc.h> -#include <dt-bindings/gpio_defines.h> -#include <dt-bindings/wake_mask_event_defines.h> -#include <nuvoton/npcx9m3f.dtsi> - -/ { - model = "NPCX9"; - - aliases { - i2c-0 = &i2c0_0; - i2c-1 = &i2c1_0; - i2c-2 = &i2c2_0; - i2c-3 = &i2c3_0; - i2c-5 = &i2c5_0; - i2c-7 = &i2c7_0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - i2c_sensor: sensor { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_SENSOR"; - label = "SENSOR"; - }; - tcpc0_2 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_USB_C0_C2_TCPC"; - label = "TCPC0,2"; - }; - tcpc1 { - i2c-port = <&i2c4_1>; - enum-name = "I2C_PORT_USB_C1_TCPC"; - label = "TCPC1"; - }; - ppc0_2 { - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_USB_C0_C2_PPC"; - label = "PPC0,2"; - }; - ppc1 { - i2c-port = <&i2c6_1>; - enum-name = "I2C_PORT_USB_C1_PPC"; - label = "PPC1"; - }; - retimer0_2 { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_USB_C0_C2_MUX"; - label = "RETIMER0,2"; - }; - battery { - i2c-port = <&i2c5_0>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - eeprom { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_EEPROM"; - label = "EEPROM"; - }; - charger { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_CHARGER"; - label = "EEPROM"; - }; - }; - - named-pwms { - compatible = "named-pwms"; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>; -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c4_1 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl4 { - status = "okay"; -}; - -&i2c5_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c6_1 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl6 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl7 { - status = "okay"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - &alt9_no_kso13_sl - &alt9_no_kso14_sl - >; -}; diff --git a/zephyr/boards/arm/npcx9/npcx9_defconfig b/zephyr/boards/arm/npcx9/npcx9_defconfig deleted file mode 100644 index d20fd87f3a..0000000000 --- a/zephyr/boards/arm/npcx9/npcx9_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX9=y -CONFIG_SOC_NPCX9M3F=y - -# Platform Configuration -CONFIG_BOARD_NPCX9=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.board b/zephyr/boards/arm/npcx_evb/Kconfig.board deleted file mode 100644 index 0ac4a80833..0000000000 --- a/zephyr/boards/arm/npcx_evb/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Note: this Zephyr board more closely represents the Chrome OS -# concept of a baseboard. Zephyr boards and Chrome OS boards do not -# have a 1:1 mapping. -config BOARD_NPCX7_EVB - bool "NPCX7 Evaluation Board" - depends on SOC_NPCX7M6FB || SOC_NPCX7M6FC || SOC_NPCX7M7FC - # Allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT - -config BOARD_NPCX9_EVB - bool "NPCX9 Evaluation Board" - depends on SOC_NPCX9M3F || SOC_NPCX9M6F - # Allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig deleted file mode 100644 index c0c874ad26..0000000000 --- a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -config BOARD - default "npcx7_evb" if BOARD_NPCX7_EVB - default "npcx9_evb" if BOARD_NPCX9_EVB diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts deleted file mode 100644 index c20589d637..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx7.dtsi> - -/* - * #include <nuvoton/npcx7m6fb.dtsi> - * #include <nuvoton/npcx7m6fc.dtsi> - * #include <nuvoton/npcx7m7fc.dtsi> - */ -#include <nuvoton/npcx7m6fc.dtsi> -#include "npcx_evb.dtsi" - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */ -}; diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig deleted file mode 100644 index b2fc879cbc..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX7=y -# NPCX7 soc list -# CONFIG_SOC_NPCX7M6FB -# CONFIG_SOC_NPCX7M6FC -# CONFIG_SOC_NPCX7M7FC -CONFIG_SOC_NPCX7M6FC=y - -# Platform Configuration -CONFIG_BOARD_NPCX7_EVB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# I2C -CONFIG_I2C=y - -# ADC -CONFIG_ADC=y -CONFIG_ADC_SHELL=n - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts deleted file mode 100644 index 4ab68cdde1..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx9.dtsi> - -/* - * #include <nuvoton/npcx9m3f.dtsi> - * #include <nuvoton/npcx9m6f.dtsi> - */ -#include <nuvoton/npcx9m6f.dtsi> -#include "npcx_evb.dtsi" - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>; -}; diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig deleted file mode 100644 index 9a946584ef..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX9=y -# NPCX9 soc list -# CONFIG_SOC_NPCX9M3F -# CONFIG_SOC_NPCX9M6F -CONFIG_SOC_NPCX9M6F=y - -# Platform Configuration -CONFIG_BOARD_NPCX9_EVB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# I2C -CONFIG_I2C=y - -# ADC -CONFIG_ADC=y -CONFIG_ADC_SHELL=n - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi deleted file mode 100644 index 61a1e79783..0000000000 --- a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <dt-bindings/gpio_defines.h> - -/ { - model = "Nuvoton NPCX Evaluation Board"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - cros,rtc = &mtc; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_evb_0_0 { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_EVB_0"; - label = "I2C0_0"; - }; - i2c_evb_1_0 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_EVB_1"; - label = "I2C1_0"; - }; - i2c_evb_2_0 { - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_EVB_2"; - label = "I2C2_0"; - }; - i2c_evb_3_0 { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_EVB_3"; - label = "I2C3_0"; - }; - i2c_evb_7_0 { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_EVB_7"; - label = "I2C7_0"; - }; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_ch_0 { - label = "ADC0"; - enum-name = "ADC_EVB_CH_0"; - channel = <0>; - }; - adc_ch_1 { - label = "ADC1"; - enum-name = "ADC_EVB_CH_1"; - channel = <1>; - }; - adc_ch_2 { - label = "ADC2"; - enum-name = "ADC_EVB_CH_2"; - channel = <2>; - }; - adc_ch_3 { - label = "ADC3"; - enum-name = "ADC_EVB_CH_3"; - channel = <3>; - }; - adc_ch_4 { - label = "ADC4"; - enum-name = "ADC_EVB_CH_4"; - channel = <4>; - }; - }; - - vsby-psl-in-list { - /* Use PSL_IN1/2/3 as detection pins from hibernate mode */ - psl-in-pads = <&psl_in1 &psl_in2 &psl_in3>; - }; -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl7 { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -/* Power switch logic input pads */ -&psl_in1 { - flag = <NPCX_PSL_FALLING_EDGE>; -}; -&psl_in2 { - flag = <NPCX_PSL_FALLING_EDGE>; -}; -&psl_in3 { - flag = <NPCX_PSL_RISING_EDGE>; -}; - -&cros_kb_raw { - status = "okay"; - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso02_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - >; -}; diff --git a/zephyr/boards/arm/trogdor/Kconfig.board b/zephyr/boards/arm/trogdor/Kconfig.board deleted file mode 100644 index 4bfa4e50ac..0000000000 --- a/zephyr/boards/arm/trogdor/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# "BOARD" below refers to a Zephyr board, which does not have a 1:1 -# mapping with the Chrome OS concept of a board. By Zephyr's -# conventions, we'll still call it "BOARD_*" to make this more -# applicable to be upstreamed, even though this code is shared by all -# projects using Trogdor baseboard. -config BOARD_TROGDOR - bool "Google Trogdor Baseboard" - depends on SOC_NPCX7M7FC - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/trogdor/Kconfig.defconfig b/zephyr/boards/arm/trogdor/Kconfig.defconfig deleted file mode 100644 index bfd2e43bbf..0000000000 --- a/zephyr/boards/arm/trogdor/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_TROGDOR - -config BOARD - default "trogdor" - -endif # BOARD_TROGDOR diff --git a/zephyr/boards/arm/trogdor/board.cmake b/zephyr/boards/arm/trogdor/board.cmake deleted file mode 100644 index a204305534..0000000000 --- a/zephyr/boards/arm/trogdor/board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin) diff --git a/zephyr/boards/arm/trogdor/trogdor.dts b/zephyr/boards/arm/trogdor/trogdor.dts deleted file mode 100644 index 4bc7f7efc1..0000000000 --- a/zephyr/boards/arm/trogdor/trogdor.dts +++ /dev/null @@ -1,272 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx7.dtsi> -#include <dt-bindings/adc/adc.h> -#include <dt-bindings/gpio_defines.h> -#include <dt-bindings/wake_mask_event_defines.h> -#include <nuvoton/npcx7m7fc.dtsi> - -/ { - model = "Google Trogdor Baseboard"; - - aliases { - i2c-0 = &i2c0_0; - i2c-1 = &i2c1_0; - i2c-2 = &i2c2_0; - i2c-3 = &i2c3_0; - i2c-5 = &i2c5_0; - i2c-7 = &i2c7_0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - cros,rtc = &mtc; - }; - - ec-console { - compatible = "ec-console"; - - disabled = "hostcmd"; - }; - - ec-mkbp-host-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <( - HOST_EVENT_MASK(HOST_EVENT_LID_OPEN) | - HOST_EVENT_MASK(HOST_EVENT_POWER_BUTTON) | - HOST_EVENT_MASK(HOST_EVENT_AC_CONNECTED) | - HOST_EVENT_MASK(HOST_EVENT_AC_DISCONNECTED) | - HOST_EVENT_MASK(HOST_EVENT_HANG_DETECT) | - HOST_EVENT_MASK(HOST_EVENT_RTC) | - HOST_EVENT_MASK(HOST_EVENT_MODE_CHANGE) | - HOST_EVENT_MASK(HOST_EVENT_DEVICE))>; - }; - - ec-mkbp-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | - MKBP_EVENT_HOST_EVENT | - MKBP_EVENT_SENSOR_FIFO)>; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - power { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_POWER"; - label = "POWER"; - }; - battery { - i2c-port = <&i2c0_0>; - remote-port = <0>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - virtual { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_VIRTUAL"; - label = "VIRTUAL"; - }; - charger { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_CHARGER"; - label = "CHARGER"; - }; - tcpc0 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_TCPC0"; - label = "TCPC0"; - }; - tcpc1 { - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_TCPC1"; - label = "TCPC1"; - }; - eeprom { - i2c-port = <&i2c5_0>; - enum-name = "I2C_PORT_EEPROM"; - label = "EEPROM"; - }; - i2c_sensor: sensor { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_SENSOR"; - label = "SENSOR"; - }; - accel { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_ACCEL"; - label = "ACCEL"; - }; - }; - - named-pwms { - compatible = "named-pwms"; - - kblight { - pwms = <&pwm3 0 0>; - label = "KBLIGHT"; - frequency = <10000>; - }; - displight { - pwms = <&pwm5 0 0>; - label = "DISPLIGHT"; - frequency = <4800>; - }; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - vbus { - label = "ADC_VBUS"; - enum-name = "ADC_VBUS"; - channel = <1>; - /* Measure VBUS through a 1/10 voltage divider */ - mul = <10>; - }; - amon_bmon { - label = "ADC_AMON_BMON"; - enum-name = "ADC_AMON_BMON"; - channel = <2>; - /* - * Adapter current output or battery charging/ - * discharging current (uV) 18x amplification on - * charger side. - */ - mul = <1000>; - div = <18>; - }; - psys { - label = "ADC_PSYS"; - enum-name = "ADC_PSYS"; - channel = <3>; - /* - * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, - * to read 0.8V @ 99 W, i.e. 124000 uW/mV. - */ - mul = <124000>; - }; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - - /* I2C_SDA0 & SCL0 */ - lvol-io-pads = <&lvol_iob4 &lvol_iob5>; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */ -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; - - isl9238: isl9238@9 { - compatible = "intersil,isl9238"; - reg = <0x09>; - label = "ISL9238_CHARGER"; - }; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - /* Not used as no WLC connected */ - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c5_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl7 { - status = "okay"; -}; - -/* Keyboard backlight */ -&pwm3 { - status = "okay"; -}; - -/* Display backlight */ -&pwm5 { - status = "okay"; -}; - -&adc0 { - status = "okay"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - >; -}; diff --git a/zephyr/boards/arm/trogdor/trogdor_defconfig b/zephyr/boards/arm/trogdor/trogdor_defconfig deleted file mode 100644 index 2a61f3dd5c..0000000000 --- a/zephyr/boards/arm/trogdor/trogdor_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX7=y -CONFIG_SOC_NPCX7M7FC=y - -# Platform Configuration -CONFIG_BOARD_TROGDOR=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y diff --git a/zephyr/boards/arm/volteer/Kconfig.board b/zephyr/boards/arm/volteer/Kconfig.board deleted file mode 100644 index 5a0390e16f..0000000000 --- a/zephyr/boards/arm/volteer/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Note: this Zephyr board more closely represents the Chrome OS -# concept of a baseboard. Zephyr boards and Chrome OS boards do not -# have a 1:1 mapping. -config BOARD_VOLTEER - bool "Google Volteer Baseboard" - depends on SOC_NPCX7M6FC || SOC_NPCX7M7FC - # NPCX doesn't actually have enough ram for coverage, but this will - # allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/arm/volteer/Kconfig.defconfig b/zephyr/boards/arm/volteer/Kconfig.defconfig deleted file mode 100644 index 05361962d9..0000000000 --- a/zephyr/boards/arm/volteer/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Google Volteer EC - -# Copyright 2020 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_VOLTEER - -config BOARD - default "volteer" - -endif # BOARD_VOLTEER diff --git a/zephyr/boards/arm/volteer/board.cmake b/zephyr/boards/arm/volteer/board.cmake deleted file mode 100644 index e29e12278d..0000000000 --- a/zephyr/boards/arm/volteer/board.cmake +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.npcx.bin) diff --git a/zephyr/boards/arm/volteer/volteer.dts b/zephyr/boards/arm/volteer/volteer.dts deleted file mode 100644 index d837f8ab55..0000000000 --- a/zephyr/boards/arm/volteer/volteer.dts +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2020 The Chromium OS Authors - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include <cros/nuvoton/npcx7.dtsi> -#include <dt-bindings/adc/adc.h> -#include <dt-bindings/charger/intersil_isl9241.h> -#include <dt-bindings/gpio_defines.h> -#include <nuvoton/npcx7m7fc.dtsi> -#include <cros/thermistor/thermistor.dtsi> - -/ { - model = "Google Volteer EC"; - - aliases { - i2c-0 = &i2c0_0; - i2c-1 = &i2c1_0; - i2c-2 = &i2c2_0; - i2c-3 = &i2c3_0; - i2c-5 = &i2c5_0; - i2c-7 = &i2c7_0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - cros,rtc = &mtc; - }; - - ec-console { - compatible = "ec-console"; - - disabled = "hostcmd"; - }; - - named-batteries { - compatible = "named-batteries"; - - lgc011 { - enum-name = "lgc011"; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_sensor: sensor { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_SENSOR"; - label = "SENSOR"; - }; - i2c-accel { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_ACCEL"; - label = "ACCEL"; - }; - usb-c0 { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_USB_C0"; - label = "USB_C0"; - }; - usb-c1 { - i2c-port = <&i2c2_0>; - enum-name = "I2C_PORT_USB_C1"; - label = "USB_C1"; - }; - usb1-mix { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_USB_1_MIX"; - label = "USB_1_MIX"; - }; - power { - i2c-port = <&i2c5_0>; - enum-name = "I2C_PORT_POWER"; - label = "POWER"; - }; - battery { - i2c-port = <&i2c5_0>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - eeprom { - i2c-port = <&i2c7_0>; - remote-port = <7>; - enum-name = "I2C_PORT_EEPROM"; - label = "EEPROM"; - }; - charger { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_CHARGER"; - label = "CHARGER"; - }; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_charger: charger { - label = "ADC_TEMP_SENSOR_CHARGER"; - enum-name = "ADC_TEMP_SENSOR_CHARGER"; - channel = <0>; - }; - adc_pp3300_regulator: pp3300_regulator { - label = "ADC_TEMP_SENSOR_PP3300_REGULATOR"; - enum-name = "ADC_TEMP_SENSOR_PP3300_REGULATOR"; - channel = <1>; - }; - adc_ddr_soc: ddr_soc { - label = "ADC_TEMP_SENSOR_DDR_SOC"; - enum-name = "ADC_TEMP_SENSOR_DDR_SOC"; - channel = <8>; - }; - adc_fan: fan { - label = "ADC_TEMP_SENSOR_FAN"; - enum-name = "ADC_TEMP_SENSOR_FAN"; - channel = <3>; - }; - }; - - named-temp-sensors { - charger { - compatible = "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "TEMP_SENSOR_CHARGER"; - enum-name = "TEMP_SENSOR_CHARGER"; - temp_fan_off = <40>; - temp_fan_max = <55>; - temp_host_high = <75>; - temp_host_halt = <80>; - temp_host_release_high = <65>; - adc = <&adc_charger>; - }; - pp3300_regulator { - compatible = "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "TEMP_SENSOR_PP3300_REGULATOR"; - enum-name = "TEMP_SENSOR_PP3300_REGULATOR"; - temp_fan_off = <40>; - temp_fan_max = <55>; - temp_host_high = <75>; - temp_host_halt = <80>; - temp_host_release_high = <65>; - adc = <&adc_pp3300_regulator>; - }; - ddr_soc { - compatible = "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "TEMP_SENSOR_DDR_SOC"; - enum-name = "TEMP_SENSOR_DDR_SOC"; - temp_fan_off = <35>; - temp_fan_max = <50>; - temp_host_high = <70>; - temp_host_halt = <80>; - temp_host_release_high = <65>; - adc = <&adc_ddr_soc>; - }; - fan { - compatible = "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "TEMP_SENSOR_FAN"; - enum-name = "TEMP_SENSOR_FAN"; - temp_fan_off = <35>; - temp_fan_max = <50>; - temp_host_high = <70>; - temp_host_halt = <80>; - temp_host_release_high = <65>; - adc = <&adc_fan>; - }; - }; - - vsby-psl-in-list { - /* Use PSL_IN1/2/3/4 as detection pins from hibernate mode */ - psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>; - }; - - /* - * The CBI Second Source Factory Cache (SSFC) layout definition. - * Specific fields values are defined per board. - */ - cbi-ssfc { - compatible = "named-cbi-ssfc"; - - cbi_ssfc_base_sensor: base_sensor { - enum-name = "BASE_SENSOR"; - size = <3>; - }; - cbi_ssfc_lid_sensor: lid_sensor { - enum-name = "LID_SENSOR"; - size = <3>; - }; - cbi_ssfc_lightbar: lightbar { - enum-name = "LIGHTBAR"; - size = <2>; - }; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */ -}; - -&i2c0_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c1_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c2_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST_PLUS>; -}; - -&i2c_ctrl2 { - status = "okay"; -}; - -&i2c3_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c5_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c7_0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; - - isl9241: isl9241@9 { - compatible = "intersil,isl9241"; - reg = <0x09>; - label = "ISL9241_CHARGER"; - switching-frequency = <SWITCHING_FREQ_724KHZ>; - }; -}; - -&i2c_ctrl7 { - status = "okay"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = <&alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - &alt9_no_kso13_sl - &alt9_no_kso14_sl - >; -}; - -&adc0 { - status = "okay"; -}; - -/* Power switch logic input pads */ -&psl_in1 { - flag = <NPCX_PSL_RISING_EDGE>; -}; - -&psl_in2 { - flag = <NPCX_PSL_RISING_EDGE>; -}; - -&psl_in3 { - flag = <NPCX_PSL_FALLING_EDGE>; -}; - -&psl_in4 { - flag = <NPCX_PSL_RISING_EDGE>; -}; - -&thermistor_3V3_30K9_47K_4050B { - status = "okay"; -}; diff --git a/zephyr/boards/arm/volteer/volteer_defconfig b/zephyr/boards/arm/volteer/volteer_defconfig deleted file mode 100644 index a3f184dff8..0000000000 --- a/zephyr/boards/arm/volteer/volteer_defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_NPCX7=y -CONFIG_SOC_NPCX7M7FC=y - -# Platform Configuration -CONFIG_BOARD_VOLTEER=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Pinmux Driver -CONFIG_PINMUX=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# ADC -# The resolution and oversamplig values are fixed by the NPCX ADC driver -CONFIG_ADC=y -CONFIG_ADC_SHELL=n - -# Power Management -CONFIG_SOC_POWER_MANAGEMENT=y -CONFIG_PM_POLICY_APP=y -CONFIG_UART_CONSOLE_INPUT_EXPIRED=y -CONFIG_SOC_POWER_MANAGEMENT_TRACE=y - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_NPCX=y |