diff options
Diffstat (limited to 'zephyr/boards/riscv')
| -rw-r--r-- | zephyr/boards/riscv/asurada/Kconfig.board | 14 | ||||
| -rw-r--r-- | zephyr/boards/riscv/asurada/Kconfig.defconfig | 56 | ||||
| -rw-r--r-- | zephyr/boards/riscv/asurada/asurada.dts | 200 | ||||
| -rw-r--r-- | zephyr/boards/riscv/asurada/asurada_defconfig | 99 | ||||
| -rw-r--r-- | zephyr/boards/riscv/it8xxx2_evb/Kconfig.board | 9 | ||||
| -rw-r--r-- | zephyr/boards/riscv/it8xxx2_evb/Kconfig.defconfig | 10 | ||||
| -rw-r--r-- | zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts | 255 | ||||
| -rw-r--r-- | zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig | 75 |
8 files changed, 0 insertions, 718 deletions
diff --git a/zephyr/boards/riscv/asurada/Kconfig.board b/zephyr/boards/riscv/asurada/Kconfig.board deleted file mode 100644 index f17a00d2fd..0000000000 --- a/zephyr/boards/riscv/asurada/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# "BOARD" below refers to a Zephyr board, which does not have a 1:1 -# mapping with the Chrome OS concept of a board. By Zephyr's -# conventions, we'll still call it "BOARD_*" to make this more -# applicable to be upstreamed, even though this code is shared by all -# projects using Trogdor baseboard. -config BOARD_ASURADA - bool "Google Asurada Baseboard" - depends on SOC_IT8XXX2 - # Allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/riscv/asurada/Kconfig.defconfig b/zephyr/boards/riscv/asurada/Kconfig.defconfig deleted file mode 100644 index cc3e4b000c..0000000000 --- a/zephyr/boards/riscv/asurada/Kconfig.defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_ASURADA - -config BOARD - default "asurada" - -# Zephyr internal stack sizes - -config IDLE_STACK_SIZE - default 256 - -config ISR_STACK_SIZE - default 800 - -config SHELL_STACK_SIZE - default 1048 - -config SYSTEM_WORKQUEUE_STACK_SIZE - default 1024 - - -# Chromium EC stack sizes - -config TASK_CHARGER_STACK_SIZE - default 960 - -config TASK_CHIPSET_STACK_SIZE - default 820 - -config TASK_HOOKS_STACK_SIZE - default 672 - -config TASK_HOSTCMD_STACK_SIZE - default 1024 - -config TASK_KEYSCAN_STACK_SIZE - default 920 - -config TASK_MOTIONSENSE_STACK_SIZE - default 920 - -config TASK_PD_STACK_SIZE - default 1024 - -config TASK_USB_CHG_STACK_SIZE - default 800 - - -choice PLATFORM_EC_HOSTCMD_DEBUG_MODE - default HCDEBUG_OFF -endchoice # PLATFORM_EC_HOSTCMD_DEBUG_MODE - -endif # BOARD_ASURADA diff --git a/zephyr/boards/riscv/asurada/asurada.dts b/zephyr/boards/riscv/asurada/asurada.dts deleted file mode 100644 index 7b4519c0e1..0000000000 --- a/zephyr/boards/riscv/asurada/asurada.dts +++ /dev/null @@ -1,200 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/ite/it8xxx2.dtsi> -#include <dt-bindings/adc/adc.h> -#include <dt-bindings/gpio_defines.h> -#include <it8xxx2.dtsi> -#include <dt-bindings/wake_mask_event_defines.h> - -/ { - model = "Google Asurada Baseboard"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - zephyr,flash-controller = &flashctrl; - }; - - ec-mkbp-host-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <( - HOST_EVENT_MASK(HOST_EVENT_AC_CONNECTED) | - HOST_EVENT_MASK(HOST_EVENT_AC_DISCONNECTED) | - HOST_EVENT_MASK(HOST_EVENT_LID_OPEN) | - HOST_EVENT_MASK(HOST_EVENT_POWER_BUTTON) | - HOST_EVENT_MASK(HOST_EVENT_HANG_DETECT) | - HOST_EVENT_MASK(HOST_EVENT_MODE_CHANGE))>; - }; - - ec-mkbp-event-wakeup-mask { - compatible = "ec-wake-mask-event"; - wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | - MKBP_EVENT_HOST_EVENT)>; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_vbus_c0 { - label = "ADC_VBUS_C0"; - enum-name = "ADC_VBUS_C0"; - channel = <0>; - mul = <10>; - }; - adc_board_id0 { - label = "ADC_BOARD_ID_0"; - enum-name = "ADC_BOARD_ID_0"; - channel = <1>; - }; - adc_board_id1 { - label = "ADC_BOARD_ID_1"; - enum-name = "ADC_BOARD_ID_1"; - channel = <2>; - }; - adc_charger_amon_r { - label = "ADC_AMON_BMON"; - enum-name = "ADC_AMON_BMON"; - channel = <3>; - mul = <1000>; - div = <18>; - }; - adc_vbus_c1 { - label = "ADC_VBUS_C1"; - enum-name = "ADC_VBUS_C1"; - channel = <5>; - mul = <10>; - }; - adc_charger_pmon { - label = "ADC_PMON"; - enum-name = "ADC_PMON"; - channel = <6>; - }; - adc-psys { - label = "ADC_PSYS"; - enum-name = "ADC_PSYS"; - channel = <6>; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - power { - i2c-port = <&i2c0>; - enum-name = "I2C_PORT_POWER"; - label = "POWER"; - }; - battery { - i2c-port = <&i2c0>; - remote-port = <0>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - eeprom { - i2c-port = <&i2c0>; - enum-name = "I2C_PORT_EEPROM"; - label = "EEPROM"; - }; - charger { - i2c-port = <&i2c0>; - enum-name = "I2C_PORT_CHARGER"; - label = "CHARGER"; - }; - i2c_sensor: sensor { - i2c-port = <&i2c1>; - enum-name = "I2C_PORT_SENSOR"; - label = "SENSOR"; - }; - i2c-accel { - i2c-port = <&i2c1>; - enum-name = "I2C_PORT_ACCEL"; - label = "ACCEL"; - }; - ppc0 { - i2c-port = <&i2c2>; - enum-name = "I2C_PORT_PPC0"; - label = "PPC0"; - }; - ppc1 { - i2c-port = <&i2c4>; - enum-name = "I2C_PORT_PPC1"; - label = "PPC1"; - }; - usb-c0 { - i2c-port = <&i2c2>; - enum-name = "I2C_PORT_USB_C0"; - label = "USB_C0"; - }; - usb-c1 { - i2c-port = <&i2c4>; - enum-name = "I2C_PORT_USB_C1"; - label = "USB_C1"; - }; - usb-mux0 { - i2c-port = <&i2c2>; - enum-name = "I2C_PORT_USB_MUX0"; - label = "USB_MUX0"; - }; - usb-mux1 { - i2c-port = <&i2c4>; - enum-name = "I2C_PORT_USB_MUX1"; - label = "USB_MUX1"; - }; - }; - - soc { - cros_kb_raw: cros-kb-raw@f01d00 { - compatible = "ite,it8xxx2-cros-kb-raw"; - reg = <0x00f01d00 0x29>; - label = "CROS_KB_RAW_0"; - interrupt-parent = <&intc>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <1804800>; -}; - -&adc0 { - status = "okay"; -}; - -&i2c0 { - /* EC_I2C_PWR_CBI */ - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c1 { - /* EC_I2C_SENSOR */ - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c2 { - /* EC_I2C_USB_C0 */ - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&i2c4{ - /* EC_I2C_USB_C1 */ - status = "okay"; - clock-frequency = <I2C_BITRATE_FAST>; -}; - -&cros_kb_raw { - status = "okay"; -}; diff --git a/zephyr/boards/riscv/asurada/asurada_defconfig b/zephyr/boards/riscv/asurada/asurada_defconfig deleted file mode 100644 index be85cd0f07..0000000000 --- a/zephyr/boards/riscv/asurada/asurada_defconfig +++ /dev/null @@ -1,99 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y - -# Platform Configuration -CONFIG_SOC_IT8XXX2=y -CONFIG_BOARD_ASURADA=y - -# SoC configuration -CONFIG_AP=y -CONFIG_AP_ARM_MTK_MT8192=y -CONFIG_HAS_TASK_CHIPSET=y - -# Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_NS16550=y -CONFIG_SHELL_TAB=y -CONFIG_SHELL_TAB_AUTOCOMPLETION=y -CONFIG_SHELL_HISTORY=y - -# GPIO Controller -CONFIG_GPIO=y -CONFIG_GPIO_ITE_IT8XXX2=y - -# ADC Driver -CONFIG_ADC_ITE_IT8XXX2=y -CONFIG_PLATFORM_EC_ADC=y -CONFIG_PLATFORM_EC_ADC_RESOLUTION=10 - -# Clock configuration -CONFIG_CLOCK_CONTROL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768 - -# Flash -CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y -CONFIG_PLATFORM_EC_FLASH_CROS=y -CONFIG_SOC_FLASH_ITE_IT8XXX2=y - -# I2C -CONFIG_I2C_ITE_IT8XXX2=y -CONFIG_PLATFORM_EC_I2C=y - -# Keyboard -CONFIG_PLATFORM_EC_KEYBOARD=y -CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y - -# Lid Switch -CONFIG_PLATFORM_EC_LID_SWITCH=y - -# MKBP -CONFIG_PLATFORM_EC_MKBP_EVENT=y -CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y -CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y -CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y - -# Pinmux Driver -CONFIG_PINMUX=y -CONFIG_PINMUX_ITE_IT8XXX2=y - -# Power Button -CONFIG_PLATFORM_EC_POWER_BUTTON=y - -# Power Sequencing -CONFIG_PLATFORM_EC_POWERSEQ=y -CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y -CONFIG_PLATFORM_EC_POWERSEQ_IT8XXX2=y -CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n -CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y -CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n -CONFIG_PLATFORM_EC_PWM=y -CONFIG_PWM_ITE_IT8XXX2=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Serial Host Interface (SHI) device. -CONFIG_CROS_SHI_IT8XXX2=y - -# Timer configuration -CONFIG_ITE_IT8XXX2_TIMER=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y -CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS=2500 -CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS=500 - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_IT8XXX2=y diff --git a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.board b/zephyr/boards/riscv/it8xxx2_evb/Kconfig.board deleted file mode 100644 index f0691edb39..0000000000 --- a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -config BOARD_IT8XXX2_EVB - bool "IT8XXX2 EV-board" - depends on SOC_IT8XXX2 - # Allow generating initial 0 line coverage. - select HAS_COVERAGE_SUPPORT diff --git a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.defconfig b/zephyr/boards/riscv/it8xxx2_evb/Kconfig.defconfig deleted file mode 100644 index de08d278de..0000000000 --- a/zephyr/boards/riscv/it8xxx2_evb/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -if BOARD_IT8XXX2_EVB - -config BOARD - default "it8xxx2_evb" - -endif # BOARD_IT8XXX2_EVB diff --git a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts b/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts deleted file mode 100644 index a1b61d02ec..0000000000 --- a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts +++ /dev/null @@ -1,255 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/dts-v1/; - -#include <cros/ite/it8xxx2.dtsi> -#include <dt-bindings/gpio_defines.h> -#include <it8xxx2.dtsi> - -/ { - model = "IT8XXX2 EV-Board"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,flash = &flash0; - zephyr,flash-controller = &flashctrl; - }; - - named-gpios { - compatible = "named-gpios"; - - power_button_l: power_button_l { - gpios = <&gpioe 4 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_POWER_BUTTON_L"; - label = "POWER_BUTTON_L"; - }; - lid_open: lid_open { - gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_LID_OPEN"; - label = "LID_OPEN"; - }; - wp_l { - gpios = <&gpioi 4 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_WP_L"; - label = "WP_L"; - }; - pch_pltrst_l { - gpios = <&gpioe 3 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_PCH_RSMRST_L"; - label = "PCH_PLTRST_L"; - }; - uart1_rx { - gpios = <&gpiob 0 GPIO_INPUT_PULL_UP>; - #enum-name = "GPIO_UART1_RX"; - label = "UART1_RX"; - }; - pch_smi_l { - gpios = <&gpiod 3 GPIO_OUT_HIGH>; - #enum-name = "GPIO_PCH_SMI_L"; - label = "PCH_SMI_L"; - }; - pch_sci_l { - gpios = <&gpiod 4 GPIO_OUT_HIGH>; - #enum-name = "GPIO_PCH_SCI_L"; - label = "PCH_SCI_L"; - }; - gate_a20_h { - gpios = <&gpiob 5 GPIO_OUT_HIGH>; - #enum-name = "GPIO_GATE_A20_H"; - label = "GATE_A20_H"; - }; - sys_reset_l { - gpios = <&gpiob 6 GPIO_OUT_HIGH>; - enum-name = "GPIO_SYS_RESET_L"; - label = "SYS_RESET_L"; - }; - lpc_clkrun_l { - gpios = <&gpioh 0 GPIO_OUT_LOW>; - #enum-name = "GPIO_LPC_CLKRUN_L"; - label = "LPC_CLKRUN_L"; - }; - pch_wake_l { - gpios = <&gpiob 7 GPIO_OUT_HIGH>; - enum-name = "GPIO_EC_PCH_WAKE_ODL"; - label = "PCH_WAKE_L"; - }; - i2c_a_scl { - gpios = <&gpiob 3 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C0_SENSOR_SCL"; - label = "I2C_A_SCL"; - }; - i2c_a_sda { - gpios = <&gpiob 4 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C0_SENSOR_SDA"; - label = "I2C_A_SDA"; - }; - i2c_b_scl { - gpios = <&gpioc 1 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C1_USB_C0_SCL"; - label = "I2C_B_SCL"; - }; - i2c_b_sda { - gpios = <&gpioc 2 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C1_USB_C0_SDA"; - label = "I2C_B_SDA"; - }; - i2c_c_scl { - gpios = <&gpiof 6 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C2_USB_C1_SCL"; - label = "I2C_C_SCL"; - }; - i2c_c_sda { - gpios = <&gpiof 7 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C2_USB_C1_SDA"; - label = "I2C_C_SDA"; - }; - i2c_e_scl { - gpios = <&gpioe 0 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C5_BATTERY_SCL"; - label = "I2C_E_SCL"; - }; - i2c_e_sda { - gpios = <&gpioe 7 GPIO_INPUT>; - enum-name = "GPIO_EC_I2C5_BATTERY_SDA"; - label = "I2C_E_SDA"; - }; - - spi0_cs { - gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; - enum-name = "GPIO_SPI0_CS"; - label = "SPI0_CS"; - }; - }; - - hibernate-wake-pins { - compatible = "cros-ec,hibernate-wake-pins"; - wakeup-pins = <&power_button_l - &lid_open>; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_vbussa: vbussa { - label = "ADC_VBUSSA"; - enum-name = "ADC_VBUS"; - channel = <0>; - }; - adc_vbussb: vbussb { - label = "ADC_VBUSSB"; - enum-name = "ADC_PSYS"; - channel = <1>; - }; - adc_evb_ch_13: evb_ch_13 { - label = "ADC_EVB_CH_13"; - enum-name = "ADC_AMON_BMON"; - channel = <2>; - }; - adc_evb_ch_14: evb_ch_14 { - label = "ADC_EVB_CH_14"; - enum-name = "ADC_TEMP_SENSOR_FAN"; - channel = <3>; - }; - adc_evb_ch_15: evb_ch_15 { - label = "ADC_EVB_CH_15"; - enum-name = "ADC_TEMP_SENSOR_DDR_SOC"; - channel = <4>; - }; - adc_evb_ch_16: evb_ch_16 { - label = "ADC_EVB_CH_16"; - enum-name = "ADC_TEMP_SENSOR_CHARGER"; - channel = <5>; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - battery { - i2c-port = <&i2c2>; - enum-name = "I2C_PORT_BATTERY"; - label = "BATTERY"; - }; - evb-1 { - i2c-port = <&i2c0>; - enum-name = "I2C_PORT_EVB_1"; - label = "EVB_1"; - }; - evb-2 { - i2c-port = <&i2c1>; - enum-name = "I2C_PORT_EVB_2"; - label = "EVB_2"; - }; - opt-4 { - i2c-port = <&i2c4>; - enum-name = "I2C_PORT_OPT_4"; - label = "OPT_4"; - }; - }; - - named-pwms { - compatible = "named-pwms"; - /* NOTE: &pwm number needs same with channel number */ - test0 { - pwms = <&pwm7 PWM_CHANNEL_7 PWM_POLARITY_INVERTED>; - label = "TEST0"; - /* - * If we need pwm output in ITE chip power saving - * mode, then we should set frequency <=324Hz. - */ - frequency = <324>; - }; - test1 { - pwms = <&pwm0 PWM_CHANNEL_0 PWM_POLARITY_NORMAL>; - label = "TEST1"; - frequency = <30000>; - }; - }; -}; - -&adc0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <I2C_BITRATE_STANDARD>; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <1804800>; -}; - -/* TEST1 */ -&pwm0 { - status = "okay"; - prescaler-cx = <PWM_PRESCALER_C6>; -}; - -/* TEST0 */ -&pwm7 { - status = "okay"; - prescaler-cx = <PWM_PRESCALER_C4>; -}; diff --git a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig b/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig deleted file mode 100644 index d667fac5a1..0000000000 --- a/zephyr/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig +++ /dev/null @@ -1,75 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y - -# Platform Configuration -CONFIG_SOC_IT8XXX2=y -CONFIG_BOARD_IT8XXX2_EVB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_NS16550=y -CONFIG_SHELL_TAB=y -CONFIG_SHELL_TAB_AUTOCOMPLETION=y -CONFIG_SHELL_HISTORY=y - -# Pinmux Driver -CONFIG_PINMUX=y -CONFIG_PINMUX_ITE_IT8XXX2=y - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n -CONFIG_PLATFORM_EC_PWM=y -CONFIG_PWM_ITE_IT8XXX2=y - -# GPIO Controller -CONFIG_GPIO=y -CONFIG_GPIO_ITE_IT8XXX2=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y -CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS=500 - -# I2C Controller -CONFIG_I2C_ITE_IT8XXX2=y - -CONFIG_ITE_IT8XXX2_TIMER=y - -# ADC -CONFIG_ADC=y -CONFIG_ADC_ITE_IT8XXX2=y -CONFIG_PLATFORM_EC_ADC_RESOLUTION=10 - -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768 - -# Flash -CONFIG_SOC_FLASH_ITE_IT8XXX2=y - -# Code RAM base for IT8XXX2 -CONFIG_CROS_EC_PROGRAM_MEMORY_BASE=0x80000000 -CONFIG_CROS_EC_RAM_BASE=0x80100000 -CONFIG_CROS_EC_DATA_RAM_SIZE=0x00100000 -CONFIG_CROS_EC_RAM_SIZE=0x0000f000 - - -CONFIG_CROS_EC_RO_MEM_OFF=0x0 -CONFIG_CROS_EC_RO_SIZE=0x80000 -CONFIG_CROS_EC_RW_MEM_OFF=0x0 -CONFIG_CROS_EC_RW_SIZE=0x80000 - -# BBRAM -CONFIG_BBRAM=y -CONFIG_BBRAM_IT8XXX2=y |