diff options
Diffstat (limited to 'zephyr/drivers/cros_rtc')
-rw-r--r-- | zephyr/drivers/cros_rtc/CMakeLists.txt | 2 | ||||
-rw-r--r-- | zephyr/drivers/cros_rtc/Kconfig | 4 | ||||
-rw-r--r-- | zephyr/drivers/cros_rtc/cros_rtc_xec.c | 6 | ||||
-rw-r--r-- | zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c | 87 | ||||
-rw-r--r-- | zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h | 76 | ||||
-rw-r--r-- | zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c | 80 | ||||
-rw-r--r-- | zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h | 84 |
7 files changed, 168 insertions, 171 deletions
diff --git a/zephyr/drivers/cros_rtc/CMakeLists.txt b/zephyr/drivers/cros_rtc/CMakeLists.txt index bfec8b9ad5..d9ae577254 100644 --- a/zephyr/drivers/cros_rtc/CMakeLists.txt +++ b/zephyr/drivers/cros_rtc/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/drivers/cros_rtc/Kconfig b/zephyr/drivers/cros_rtc/Kconfig index 50a4d00022..2839b03c62 100644 --- a/zephyr/drivers/cros_rtc/Kconfig +++ b/zephyr/drivers/cros_rtc/Kconfig @@ -1,8 +1,8 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -if PLATFORM_EC_RTC +if PLATFORM_EC_RTC && !ARCH_POSIX choice CROS_RTC_TYPE prompt "Select the RTC to use" diff --git a/zephyr/drivers/cros_rtc/cros_rtc_xec.c b/zephyr/drivers/cros_rtc/cros_rtc_xec.c index ec8e0e6d07..c543aab6af 100644 --- a/zephyr/drivers/cros_rtc/cros_rtc_xec.c +++ b/zephyr/drivers/cros_rtc/cros_rtc_xec.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -123,7 +123,7 @@ static const struct cros_rtc_xec_config cros_rtc_xec_cfg_0 = { static struct cros_rtc_xec_data cros_rtc_xec_data_0; -DEVICE_DT_INST_DEFINE(0, cros_rtc_xec_init, NULL, - &cros_rtc_xec_data_0, &cros_rtc_xec_cfg_0, POST_KERNEL, +DEVICE_DT_INST_DEFINE(0, cros_rtc_xec_init, NULL, &cros_rtc_xec_data_0, + &cros_rtc_xec_cfg_0, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &cros_rtc_xec_driver_api); diff --git a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c index e7821c1dac..c5580eaeef 100644 --- a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c +++ b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -58,12 +58,12 @@ static int pcf85063a_read_time_regs(const struct device *dev, bool is_alarm) num_reg = NUM_TIMER_REGS; } - return i2c_burst_read(config->bus, - config->i2c_addr_flags, start_reg, data->time_reg, num_reg); + return i2c_burst_read(config->bus, config->i2c_addr_flags, start_reg, + data->time_reg, num_reg); } -static int pcf85063a_read_reg(const struct device *dev, - uint8_t reg, uint8_t *val) +static int pcf85063a_read_reg(const struct device *dev, uint8_t reg, + uint8_t *val) { const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev); @@ -95,13 +95,12 @@ static int pcf85063a_write_time_regs(const struct device *dev, bool is_alarm) tx_buf[i] = data->time_reg[i]; } - return i2c_burst_write(config->bus, - config->i2c_addr_flags, start_reg, tx_buf, num_reg); + return i2c_burst_write(config->bus, config->i2c_addr_flags, start_reg, + tx_buf, num_reg); } - -static int pcf85063a_write_reg(const struct device *dev, - uint8_t reg, uint8_t val) +static int pcf85063a_write_reg(const struct device *dev, uint8_t reg, + uint8_t val) { const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev); uint8_t tx_buf[2]; @@ -109,8 +108,8 @@ static int pcf85063a_write_reg(const struct device *dev, tx_buf[0] = reg; tx_buf[1] = val; - return i2c_write(config->bus, - tx_buf, sizeof(tx_buf), config->i2c_addr_flags); + return i2c_write(config->bus, tx_buf, sizeof(tx_buf), + config->i2c_addr_flags); } /* @@ -138,7 +137,7 @@ static uint8_t dec_to_bcd(uint32_t val, enum bcd_mask mask) } static int nxp_rtc_pcf85063a_read_seconds(const struct device *dev, - uint32_t *value, bool is_alarm) + uint32_t *value, bool is_alarm) { struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev); struct calendar_date time; @@ -152,31 +151,30 @@ static int nxp_rtc_pcf85063a_read_seconds(const struct device *dev, if (is_alarm) { *value = (bcd_to_dec(data->time_reg[DAYS], DAYS_MASK) * - SECS_PER_DAY) + - (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) * - SECS_PER_HOUR) + - (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) * - SECS_PER_MINUTE) + - bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK); + SECS_PER_DAY) + + (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) * + SECS_PER_HOUR) + + (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) * + SECS_PER_MINUTE) + + bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK); } else { time.year = bcd_to_dec(data->time_reg[YEARS], YEARS_MASK); - time.month = - bcd_to_dec(data->time_reg[MONTHS], MONTHS_MASK); + time.month = bcd_to_dec(data->time_reg[MONTHS], MONTHS_MASK); time.day = bcd_to_dec(data->time_reg[DAYS], DAYS_MASK); *value = date_to_sec(time) - SECS_TILL_YEAR_2K + - (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) * - SECS_PER_HOUR) + - (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) * - SECS_PER_MINUTE) + - bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK); + (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) * + SECS_PER_HOUR) + + (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) * + SECS_PER_MINUTE) + + bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK); } return ret; } static int nxp_rtc_pcf85063a_write_seconds(const struct device *dev, - uint32_t value, bool is_alarm) + uint32_t value, bool is_alarm) { struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev); struct calendar_date time; @@ -186,8 +184,7 @@ static int nxp_rtc_pcf85063a_write_seconds(const struct device *dev, if (!is_alarm) { data->time_reg[YEARS] = dec_to_bcd(time.year, YEARS_MASK); - data->time_reg[MONTHS] = - dec_to_bcd(time.month, MONTHS_MASK); + data->time_reg[MONTHS] = dec_to_bcd(time.month, MONTHS_MASK); } data->time_reg[DAYS] = dec_to_bcd(time.day, DAYS_MASK); @@ -223,7 +220,7 @@ static int nxp_rtc_pcf85063a_write_seconds(const struct device *dev, } static int nxp_rtc_pcf85063a_configure(const struct device *dev, - cros_rtc_alarm_callback_t callback) + cros_rtc_alarm_callback_t callback) { struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev); @@ -237,7 +234,7 @@ static int nxp_rtc_pcf85063a_configure(const struct device *dev, } static int nxp_rtc_pcf85063a_get_value(const struct device *dev, - uint32_t *value) + uint32_t *value) { return nxp_rtc_pcf85063a_read_seconds(dev, value, false); } @@ -248,7 +245,8 @@ static int nxp_rtc_pcf85063a_set_value(const struct device *dev, uint32_t value) } static int nxp_rtc_pcf85063a_get_alarm(const struct device *dev, - uint32_t *seconds, uint32_t *microseconds) + uint32_t *seconds, + uint32_t *microseconds) { *microseconds = 0; return nxp_rtc_pcf85063a_read_seconds(dev, seconds, true); @@ -275,7 +273,7 @@ static int nxp_rtc_pcf85063a_reset_alarm(const struct device *dev) } static int nxp_rtc_pcf85063a_set_alarm(const struct device *dev, - uint32_t seconds, uint32_t microseconds) + uint32_t seconds, uint32_t microseconds) { int ret; @@ -297,7 +295,7 @@ static int nxp_rtc_pcf85063a_set_alarm(const struct device *dev, } static void nxp_pcf85063a_isr(const struct device *port, - struct gpio_callback *cb, uint32_t pin) + struct gpio_callback *cb, uint32_t pin) { struct nxp_rtc_pcf85063a_data *data = CONTAINER_OF(cb, struct nxp_rtc_pcf85063a_data, gpio_cb); @@ -400,8 +398,8 @@ static int nxp_rtc_pcf85063a_init(const struct device *dev) return ret; } - gpio_init_callback(&data->gpio_cb, - nxp_pcf85063a_isr, BIT(config->gpio_alert.pin)); + gpio_init_callback(&data->gpio_cb, nxp_pcf85063a_isr, + BIT(config->gpio_alert.pin)); ret = gpio_add_callback(config->gpio_alert.port, &data->gpio_cb); @@ -416,8 +414,7 @@ static int nxp_rtc_pcf85063a_init(const struct device *dev) GPIO_INT_EDGE_FALLING); } -#define PCF85063A_INT_GPIOS \ - DT_PHANDLE(DT_NODELABEL(pcf85063a), int_pin) +#define PCF85063A_INT_GPIOS DT_PHANDLE(DT_NODELABEL(pcf85063a), int_pin) /* * dt_flags is a uint8_t type. However, for platform/ec @@ -426,19 +423,17 @@ static int nxp_rtc_pcf85063a_init(const struct device *dev) * Cast back to a gpio_dt_flags to compile, discarding the bits * that are not supported by the Zephyr GPIO API. */ -#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop) \ - { \ - .port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)), \ - .pin = DT_GPIO_PIN(node_id, prop), \ - .dt_flags = \ - (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \ +#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop) \ + { \ + .port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)), \ + .pin = DT_GPIO_PIN(node_id, prop), \ + .dt_flags = (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \ } static const struct nxp_rtc_pcf85063a_config nxp_rtc_pcf85063a_cfg_0 = { .bus = DEVICE_DT_GET(DT_INST_BUS(0)), .i2c_addr_flags = DT_INST_REG_ADDR(0), - .gpio_alert = - CROS_EC_GPIO_DT_SPEC_GET(PCF85063A_INT_GPIOS, gpios) + .gpio_alert = CROS_EC_GPIO_DT_SPEC_GET(PCF85063A_INT_GPIOS, gpios) }; static struct nxp_rtc_pcf85063a_data nxp_rtc_pcf85063a_data_0; diff --git a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h index dc4fcd24fc..54b1fbd2ea 100644 --- a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h +++ b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -6,53 +6,53 @@ #ifndef __CROS_EC_RTC_PCF85063A_H #define __CROS_EC_RTC_PCF85063A_H -#define PCF85063A_REG_NUM 18 -#define SOFT_RESET 0x58 +#define PCF85063A_REG_NUM 18 +#define SOFT_RESET 0x58 #define CONTROL_1_DEFAULT_VALUE 0 -#define OS_BIT 0x80 -#define DISABLE_ALARM 0x80 -#define ENABLE_ALARM_INTERRUPT 0x80 -#define RTC_STOP_CLOCKS 0x20 -#define RTC_START_CLOCKS 0x00 +#define OS_BIT 0x80 +#define DISABLE_ALARM 0x80 +#define ENABLE_ALARM_INTERRUPT 0x80 +#define RTC_STOP_CLOCKS 0x20 +#define RTC_START_CLOCKS 0x00 -#define NUM_TIMER_REGS 7 -#define NUM_ALARM_REGS 4 +#define NUM_TIMER_REGS 7 +#define NUM_ALARM_REGS 4 -#define REG_CONTROL_1 0x00 -#define REG_CONTROL_2 0x01 -#define REG_OFFSET 0x02 -#define REG_RAM_BYTE 0x03 -#define REG_SECONDS 0x04 -#define REG_MINUTES 0x05 -#define REG_HOURS 0x06 -#define REG_DAYS 0x07 -#define REG_WEEKDAYS 0x08 -#define REG_MONTHS 0x09 -#define REG_YEARS 0x0a -#define REG_SECOND_ALARM 0x0b -#define REG_MINUTE_ALARM 0x0c -#define REG_HOUR_ALARM 0x0d -#define REG_DAY_ALARM 0x0e -#define REG_WEEKDAY_ALARM 0x0f -#define REG_TIMER_VALUE 0x10 -#define REG_TIMER_MODE 0x11 +#define REG_CONTROL_1 0x00 +#define REG_CONTROL_2 0x01 +#define REG_OFFSET 0x02 +#define REG_RAM_BYTE 0x03 +#define REG_SECONDS 0x04 +#define REG_MINUTES 0x05 +#define REG_HOURS 0x06 +#define REG_DAYS 0x07 +#define REG_WEEKDAYS 0x08 +#define REG_MONTHS 0x09 +#define REG_YEARS 0x0a +#define REG_SECOND_ALARM 0x0b +#define REG_MINUTE_ALARM 0x0c +#define REG_HOUR_ALARM 0x0d +#define REG_DAY_ALARM 0x0e +#define REG_WEEKDAY_ALARM 0x0f +#define REG_TIMER_VALUE 0x10 +#define REG_TIMER_MODE 0x11 /* Macros for indexing time_reg buffer */ -#define SECONDS 0 -#define MINUTES 1 -#define HOURS 2 -#define DAYS 3 -#define WEEKDAYS 4 -#define MONTHS 5 -#define YEARS 6 +#define SECONDS 0 +#define MINUTES 1 +#define HOURS 2 +#define DAYS 3 +#define WEEKDAYS 4 +#define MONTHS 5 +#define YEARS 6 enum bcd_mask { SECONDS_MASK = 0x70, MINUTES_MASK = 0x70, HOURS24_MASK = 0x30, - DAYS_MASK = 0x30, - MONTHS_MASK = 0x10, - YEARS_MASK = 0xf0 + DAYS_MASK = 0x30, + MONTHS_MASK = 0x10, + YEARS_MASK = 0xf0 }; #endif /* __CROS_EC_RTC_PCF85063A_H */ diff --git a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c index 661268ee9b..7a9a11fd41 100644 --- a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c +++ b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -43,8 +43,8 @@ enum timer_type { * type == RTC_TIMER: Reads time registers SECONDS, MINUTES, HOURS, DAYS, and * MONTHS, YEARS */ -static int idt1337ag_read_time_regs(const struct device *dev, - uint8_t *time_reg, enum timer_type type) +static int idt1337ag_read_time_regs(const struct device *dev, uint8_t *time_reg, + enum timer_type type) { const struct renesas_rtc_idt1337ag_config *const config = dev->config; uint8_t start_reg; @@ -58,12 +58,12 @@ static int idt1337ag_read_time_regs(const struct device *dev, num_reg = NUM_TIMER_REGS; } - return i2c_burst_read(config->bus, - config->i2c_addr_flags, start_reg, time_reg, num_reg); + return i2c_burst_read(config->bus, config->i2c_addr_flags, start_reg, + time_reg, num_reg); } -static int idt1337ag_read_reg(const struct device *dev, - uint8_t reg, uint8_t *val) +static int idt1337ag_read_reg(const struct device *dev, uint8_t reg, + uint8_t *val) { const struct renesas_rtc_idt1337ag_config *const config = dev->config; @@ -97,12 +97,12 @@ static int idt1337ag_write_time_regs(const struct device *dev, num_reg = NUM_TIMER_REGS; } - return i2c_burst_write(config->bus, - config->i2c_addr_flags, start_reg, time_reg, num_reg); + return i2c_burst_write(config->bus, config->i2c_addr_flags, start_reg, + time_reg, num_reg); } -static int idt1337ag_write_reg(const struct device *dev, - uint8_t reg, uint8_t val) +static int idt1337ag_write_reg(const struct device *dev, uint8_t reg, + uint8_t val) { const struct renesas_rtc_idt1337ag_config *const config = dev->config; uint8_t tx_buf[2]; @@ -110,8 +110,8 @@ static int idt1337ag_write_reg(const struct device *dev, tx_buf[0] = reg; tx_buf[1] = val; - return i2c_write(config->bus, - tx_buf, sizeof(tx_buf), config->i2c_addr_flags); + return i2c_write(config->bus, tx_buf, sizeof(tx_buf), + config->i2c_addr_flags); } /* @@ -139,7 +139,8 @@ static uint8_t dec_to_bcd(uint32_t val, enum bcd_mask mask) } static int renesas_rtc_idt1337ag_read_seconds(const struct device *dev, - uint32_t *value, enum timer_type type) + uint32_t *value, + enum timer_type type) { uint8_t time_reg[NUM_TIMER_REGS]; struct calendar_date time; @@ -152,12 +153,12 @@ static int renesas_rtc_idt1337ag_read_seconds(const struct device *dev, } if (type == ALARM_TIMER) { - *value = (bcd_to_dec(time_reg[DAYS], DAYS_MASK) * - SECS_PER_DAY) + + *value = + (bcd_to_dec(time_reg[DAYS], DAYS_MASK) * SECS_PER_DAY) + (bcd_to_dec(time_reg[HOURS], HOURS24_MASK) * - SECS_PER_HOUR) + + SECS_PER_HOUR) + (bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) * - SECS_PER_MINUTE) + + SECS_PER_MINUTE) + bcd_to_dec(time_reg[SECONDS], SECONDS_MASK); } else { time.year = bcd_to_dec(time_reg[YEARS], YEARS_MASK); @@ -165,18 +166,19 @@ static int renesas_rtc_idt1337ag_read_seconds(const struct device *dev, time.day = bcd_to_dec(time_reg[DAYS], DAYS_MASK); *value = date_to_sec(time) - SECS_TILL_YEAR_2K + - (bcd_to_dec(time_reg[HOURS], HOURS24_MASK) * - SECS_PER_HOUR) + - (bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) * - SECS_PER_MINUTE) + - bcd_to_dec(time_reg[SECONDS], SECONDS_MASK); + (bcd_to_dec(time_reg[HOURS], HOURS24_MASK) * + SECS_PER_HOUR) + + (bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) * + SECS_PER_MINUTE) + + bcd_to_dec(time_reg[SECONDS], SECONDS_MASK); } return ret; } static int renesas_rtc_idt1337ag_write_seconds(const struct device *dev, - uint32_t value, enum timer_type type) + uint32_t value, + enum timer_type type) { uint8_t time_reg[NUM_TIMER_REGS]; struct calendar_date time; @@ -206,7 +208,7 @@ static int renesas_rtc_idt1337ag_write_seconds(const struct device *dev, } static int renesas_rtc_idt1337ag_configure(const struct device *dev, - cros_rtc_alarm_callback_t callback) + cros_rtc_alarm_callback_t callback) { struct renesas_rtc_idt1337ag_data *data = dev->data; @@ -232,7 +234,8 @@ static int renesas_rtc_idt1337ag_set_value(const struct device *dev, } static int renesas_rtc_idt1337ag_get_alarm(const struct device *dev, - uint32_t *seconds, uint32_t *microseconds) + uint32_t *seconds, + uint32_t *microseconds) { *microseconds = 0; return renesas_rtc_idt1337ag_read_seconds(dev, seconds, ALARM_TIMER); @@ -283,7 +286,8 @@ static int renesas_rtc_idt1337ag_reset_alarm(const struct device *dev) } static int renesas_rtc_idt1337ag_set_alarm(const struct device *dev, - uint32_t seconds, uint32_t microseconds) + uint32_t seconds, + uint32_t microseconds) { int ret; uint8_t val; @@ -429,8 +433,8 @@ static int renesas_rtc_idt1337ag_init(const struct device *dev) return ret; } - gpio_init_callback(&data->gpio_cb, - renesas_rtc_idt1337ag_isr, BIT(config->gpio_alert.pin)); + gpio_init_callback(&data->gpio_cb, renesas_rtc_idt1337ag_isr, + BIT(config->gpio_alert.pin)); ret = gpio_add_callback(config->gpio_alert.port, &data->gpio_cb); @@ -445,8 +449,7 @@ static int renesas_rtc_idt1337ag_init(const struct device *dev) GPIO_INT_EDGE_FALLING); } -#define IDT1337AG_INT_PIN \ - DT_PHANDLE(DT_NODELABEL(idt1337ag), int_pin) +#define IDT1337AG_INT_PIN DT_PHANDLE(DT_NODELABEL(idt1337ag), int_pin) /* * dt_flags is a uint8_t type. However, for platform/ec @@ -455,12 +458,11 @@ static int renesas_rtc_idt1337ag_init(const struct device *dev) * Cast back to a gpio_dt_flags to compile, discarding the bits * that are not supported by the Zephyr GPIO API. */ -#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop) \ - { \ - .port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)), \ - .pin = DT_GPIO_PIN(node_id, prop), \ - .dt_flags = \ - (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \ +#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop) \ + { \ + .port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)), \ + .pin = DT_GPIO_PIN(node_id, prop), \ + .dt_flags = (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \ } static const struct renesas_rtc_idt1337ag_config renesas_rtc_idt1337ag_cfg_0 = { @@ -473,6 +475,6 @@ static struct renesas_rtc_idt1337ag_data renesas_rtc_idt1337ag_data_0; DEVICE_DT_INST_DEFINE(0, renesas_rtc_idt1337ag_init, /* pm_control_fn= */ NULL, &renesas_rtc_idt1337ag_data_0, - &renesas_rtc_idt1337ag_cfg_0, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, + &renesas_rtc_idt1337ag_cfg_0, POST_KERNEL, + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &renesas_rtc_idt1337ag_driver_api); diff --git a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h index 3296f80992..9dd195e8c3 100644 --- a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h +++ b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,54 +7,54 @@ #define __CROS_EC_RTC_IDT1337AG_H /* Setting bit 6 of register 0Ah selects the DAY as alarm source */ -#define SELECT_DAYS_ALARM 0x40 -#define DISABLE_ALARM 0x80 - -#define CONTROL_A1IE BIT(0) -#define CONTROL_A2IE BIT(1) -#define CONTROL_INTCN BIT(2) -#define CONTROL_EOSC BIT(7) - -#define STATUS_A1F BIT(0) -#define STATUS_A2F BIT(1) -#define STATUS_OSF BIT(7) - -#define NUM_TIMER_REGS 7 -#define NUM_ALARM_REGS 4 - -#define REG_SECONDS 0x00 -#define REG_MINUTES 0x01 -#define REG_HOURS 0x02 -#define REG_DAYS 0x03 -#define REG_DATE 0x04 -#define REG_MONTHS 0x05 -#define REG_YEARS 0x06 -#define REG_SECOND_ALARM1 0x07 -#define REG_MINUTE_ALARM1 0x08 -#define REG_HOUR_ALARM1 0x09 -#define REG_DAY_ALARM1 0x0a -#define REG_MINUTE_ALARM2 0x0b -#define REG_HOUR_ALARM2 0x0c -#define REG_DAY_ALARM2 0x0d -#define REG_CONTROL 0x0e -#define REG_STATUS 0x0f +#define SELECT_DAYS_ALARM 0x40 +#define DISABLE_ALARM 0x80 + +#define CONTROL_A1IE BIT(0) +#define CONTROL_A2IE BIT(1) +#define CONTROL_INTCN BIT(2) +#define CONTROL_EOSC BIT(7) + +#define STATUS_A1F BIT(0) +#define STATUS_A2F BIT(1) +#define STATUS_OSF BIT(7) + +#define NUM_TIMER_REGS 7 +#define NUM_ALARM_REGS 4 + +#define REG_SECONDS 0x00 +#define REG_MINUTES 0x01 +#define REG_HOURS 0x02 +#define REG_DAYS 0x03 +#define REG_DATE 0x04 +#define REG_MONTHS 0x05 +#define REG_YEARS 0x06 +#define REG_SECOND_ALARM1 0x07 +#define REG_MINUTE_ALARM1 0x08 +#define REG_HOUR_ALARM1 0x09 +#define REG_DAY_ALARM1 0x0a +#define REG_MINUTE_ALARM2 0x0b +#define REG_HOUR_ALARM2 0x0c +#define REG_DAY_ALARM2 0x0d +#define REG_CONTROL 0x0e +#define REG_STATUS 0x0f /* Macros for indexing time_reg buffer */ -#define SECONDS 0 -#define MINUTES 1 -#define HOURS 2 -#define DAYS 3 -#define DATE 4 -#define MONTHS 5 -#define YEARS 6 +#define SECONDS 0 +#define MINUTES 1 +#define HOURS 2 +#define DAYS 3 +#define DATE 4 +#define MONTHS 5 +#define YEARS 6 enum bcd_mask { SECONDS_MASK = 0x70, MINUTES_MASK = 0x70, HOURS24_MASK = 0x30, - DAYS_MASK = 0x00, - MONTHS_MASK = 0x10, - YEARS_MASK = 0xf0 + DAYS_MASK = 0x00, + MONTHS_MASK = 0x10, + YEARS_MASK = 0xf0 }; #endif /* __CROS_EC_RTC_IDT1337AG_H */ |