diff options
Diffstat (limited to 'zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts')
| -rw-r--r-- | zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts new file mode 100644 index 0000000000..d7bb40fad2 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts @@ -0,0 +1,100 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/ { + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_lid_open: lid-open { + irq-pin = <&smc_lid>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_power_button: power-button { + irq-pin = <&mech_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_ac_present: ac-present { + irq-pin = <&bc_acok>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_slp_s0: slp-s0 { + irq-pin = <&pch_slp_s0_n>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_slp_sus: slp-sus { + irq-pin = <&pm_slp_sus_ec_n>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_pg_dsw_pwrok: pg-dsw-pwrok { + irq-pin = <&vccpdsw_3p3>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_rsmrst_pwrgd: rsmrst-pwrgd { + irq-pin = <&rsmrst_pwrgd>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_all_sys_pwrgd: all-sys-pwrgd { + irq-pin = <&all_sys_pwrgd>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 { + irq-pin = <&usbc_tcpc_alrt_p0>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usbc_tcpc_alrt_p1: usbc-tcpc-alrt-p1 { + irq-pin = <&usbc_tcpc_alrt_p1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 { + irq-pin = <&usbc_tcpc_alrt_p2>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 { + irq-pin = <&usbc_tcpc_alrt_p3>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 { + irq-pin = <&usbc_tcpc_ppc_alrt_p0>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 { + irq-pin = <&usbc_tcpc_ppc_alrt_p1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 { + irq-pin = <&usbc_tcpc_ppc_alrt_p2>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usbc_tcpc_ppc_alrt_p3: usbc-tcpc-ppc-alrt-p3 { + irq-pin = <&usbc_tcpc_ppc_alrt_p3>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_std_adp_prsnt: std-adp-prsnt { + irq-pin = <&std_adp_prsnt>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "board_dc_jack_interrupt"; + }; + int_ccd_mode_odl: ccd-mode-odl { + irq-pin = <&ccd_mode_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "board_connect_c0_sbu"; + }; + }; +}; |