diff options
Diffstat (limited to 'zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h')
| -rw-r--r-- | zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h | 30 |
1 files changed, 14 insertions, 16 deletions
diff --git a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h index 0061b11110..135fd4ef4f 100644 --- a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h +++ b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,27 +10,25 @@ #include "config.h" +#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 +#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 -#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 -#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 - -#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 - +#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 /* SOC side BB retimers (dual retimer config) */ -#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 +#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 #if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 +#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 #endif -#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 -#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 -#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 -#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 -#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 -#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 -#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 -#define ADL_RVP_BOARD_ID(id) ((id) & 0x3F) +#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 +#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 +#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 +#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 +#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 +#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 +#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 +#define ADL_RVP_BOARD_ID(id) ((id)&0x3F) #define CONFIG_BATTERY_TYPE_NO_AUTO_DETECT |