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Diffstat (limited to 'zephyr/projects/intelrvp/adlrvp/ioex.dts')
-rw-r--r--zephyr/projects/intelrvp/adlrvp/ioex.dts78
1 files changed, 78 insertions, 0 deletions
diff --git a/zephyr/projects/intelrvp/adlrvp/ioex.dts b/zephyr/projects/intelrvp/adlrvp/ioex.dts
new file mode 100644
index 0000000000..3e2227dacb
--- /dev/null
+++ b/zephyr/projects/intelrvp/adlrvp/ioex.dts
@@ -0,0 +1,78 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+ /* IOEX_C0_PCA9675 */
+ ioex-c0 {
+ compatible = "cros,ioex-chip";
+ i2c-port = <&typec_0>;
+ i2c-addr = <0x21>;
+ drv = "pca9675_ioexpander_drv";
+ flags = <0x00>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ioex_c0_port: ioex-c0-port@0 {
+ compatible = "cros,ioex-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ };
+ };
+
+ /* IOEX_C1_PCA9675 */
+ ioex-c1 {
+ compatible = "cros,ioex-chip";
+ i2c-port = <&typec_1>;
+ i2c-addr = <0x21>;
+ drv = "pca9675_ioexpander_drv";
+ flags = <0x00>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ioex_c1_port: ioex-c1-port@0 {
+ compatible = "cros,ioex-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ };
+ };
+
+ /* IOEX_C2_PCA9675 */
+ ioex-c2 {
+ compatible = "cros,ioex-chip";
+ i2c-port = <&typec_2>;
+ i2c-addr = <0x21>;
+ drv = "pca9675_ioexpander_drv";
+ flags = <0x00>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ioex_c2_port: ioex-c2-port@0 {
+ compatible = "cros,ioex-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ };
+ };
+
+ /* IOEX_C3_PCA9675 */
+ ioex-c3 {
+ compatible = "cros,ioex-chip";
+ i2c-port = <&typec_3>;
+ i2c-addr = <0x21>;
+ drv = "pca9675_ioexpander_drv";
+ flags = <0x00>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ioex_c3_port: ioex-c3-port@0 {
+ compatible = "cros,ioex-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ };
+ };
+};