1 files changed, 105 insertions, 0 deletions
diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts
new file mode 100644
index 0000000000..c55c57a655
--- /dev/null
+++ b/zephyr/projects/skyrim/skyrim.dts
@@ -0,0 +1,105 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-gpios {
+		/* Skyrim-specific GPIO customizations */
+		usb_fault_odl {
+			gpios = <&gpio5 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_USB_FAULT_ODL";
+		};
+		en_pwr_s3 {
+			gpios = <&gpio7 4 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EN_PWR_S3";
+		};
+		pg_groupc_s0_od {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+			enum-name = "GPIO_PG_GROUPC_S0_OD";
+		};
+		/* TODO: Add interrupt handler */
+		ec_i2c_usbc_pd_int {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_EC_I2C_USBC_PD_INT";
+		};
+		/* TODO: Add interrupt handler */
+		soc_thermtrip_odl {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+			enum-name = "GPIO_SOC_THERMTRIP_ODL";
+		};
+		hub_rst {
+			gpios = <&gpio6 6 GPIO_OUT_LOW>;
+			enum-name = "GPIO_HUB_RST";
+		};
+		ec_soc_int_l {
+			gpios = <&gpioa 1 GPIO_OUT_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		ec_soc_pwr_good {
+			gpios = <&gpiod 3 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EC_SOC_PWR_GOOD";
+		};
+		/* TODO: Add interrupt handler to shut down */
+		pcore_ocp_r_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+			enum-name = "GPIO_PCORE_OCP_L";
+		};
+		/* TODO: Add interrupt handler */
+		sc_0_int_l {
+			gpios = <&gpio6 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_SC_0_INT_L";
+		};
+		/* TODO: Add interrupt handler */
+		usb_hub_fault_q_odl {
+			gpios = <&gpioe 5 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_USB_HUB_FAULT_ODL";
+		};
+		pg_lpddr5_s3_od {
+			gpios = <&gpio7 3 GPIO_INPUT>;
+			enum-name = "GPIO_PG_LPDDR5_S3_OD";
+		};
+		3axis_int_l {
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+		};
+		ec_soc_pwr_btn_l {
+			gpios = <&gpioa 7 GPIO_OUT_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		volup_btn_odl {
+			gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		voldn_btn_odl {
+			gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		ec_sc_rst {
+			gpios = <&gpiob 0 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EC_SC_RST";
+		};
+		/* TODO: Add CBI_WP feature config */
+		ec_cbi_wp {
+			gpios = <&gpio8 1 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EC_CBI_WP";
+		};
+		ec_wp_l {
+			gpios = <&gpiod 7 GPIO_INPUT>;
+			enum-name = "GPIO_WP_L";
+		};
+		pg_lpddr5_s0_od {
+			gpios = <&gpio6 0 GPIO_INPUT>;
+			enum-name = "GPIO_PG_LPDDR5_S0_OD";
+		};
+	};
+
+	def-lvol-io-list {
+		compatible = "nuvoton,npcx-lvolctrl-def";
+
+		/*
+		 * Low voltage on I2C2_0, I2C6_1, I2C7_0, USB_FAUT_ODL
+		 */
+		lvol-io-pads = <&lvol_io92 &lvol_io91 &lvol_ioe4 &lvol_ioe3
+				&lvol_iob3 &lvol_iob2 &lvol_io50>;
+	};
+};