diff options
Diffstat (limited to 'zephyr/projects')
| -rw-r--r-- | zephyr/projects/intelrvp/BUILD.py | 40 | ||||
| -rw-r--r-- | zephyr/projects/intelrvp/CMakeLists.txt | 10 | ||||
| -rw-r--r-- | zephyr/projects/intelrvp/Kconfig | 12 | ||||
| -rw-r--r-- | zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts | 14 | ||||
| -rw-r--r-- | zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts | 10 | ||||
| -rw-r--r-- | zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts | 20 | ||||
| -rw-r--r-- | zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf | 8 | ||||
| -rw-r--r-- | zephyr/projects/intelrvp/adlrvp/prj.conf | 3 | ||||
| -rw-r--r-- | zephyr/projects/intelrvp/include/gpio_map.h | 9 | ||||
| -rw-r--r-- | zephyr/projects/intelrvp/prj.conf | 21 |
10 files changed, 144 insertions, 3 deletions
diff --git a/zephyr/projects/intelrvp/BUILD.py b/zephyr/projects/intelrvp/BUILD.py new file mode 100644 index 0000000000..d1eeaf6693 --- /dev/null +++ b/zephyr/projects/intelrvp/BUILD.py @@ -0,0 +1,40 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# intelrvp has adlrvp_npcx, adlrvpp_ite, adlrvpp_mchp etc + + +def register_intelrvp_project( + project_name, + chip="npcx9", + extra_dts_overlays=(), + extra_kconfig_files=(), +): + register_func = register_binman_project + if chip.startswith("npcx9"): + register_func = register_npcx_project + + kconfig_files = [here / "prj.conf"] + if project_name.startswith("adlrvp"): + kconfig_files.append(here / "adlrvp/prj.conf") + kconfig_files.extend(extra_kconfig_files) + + register_func( + project_name=project_name, + zephyr_board=chip, + dts_overlays=extra_dts_overlays, + kconfig_files=kconfig_files, + ) + + +register_intelrvp_project( + project_name="adlrvp_npcx", + chip="npcx9", + extra_dts_overlays=[ + here / "adlrvp/adlrvp_npcx/adlrvp_npcx.dts", + here / "adlrvp/adlrvp_npcx/gpio.dts", + here / "adlrvp/adlrvp_npcx/interrupts.dts", + ], + extra_kconfig_files=[here / "adlrvp/adlrvp_npcx/prj.conf"], +) diff --git a/zephyr/projects/intelrvp/CMakeLists.txt b/zephyr/projects/intelrvp/CMakeLists.txt new file mode 100644 index 0000000000..7b8cdde779 --- /dev/null +++ b/zephyr/projects/intelrvp/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(intelrvp) + +zephyr_include_directories(include) diff --git a/zephyr/projects/intelrvp/Kconfig b/zephyr/projects/intelrvp/Kconfig new file mode 100644 index 0000000000..0a1f40bfdd --- /dev/null +++ b/zephyr/projects/intelrvp/Kconfig @@ -0,0 +1,12 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +config BOARD_ADLRVP_NPCX + bool "Intel ADLRVP_NPCX board" + depends on SOC_NPCX9M3F + help + Build Intel ADLRVP_NPCX reference board. This board has Intel ADL RVP + SoC with NPCX9M3F EC. + +source "Kconfig.zephyr" diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts new file mode 100644 index 0000000000..ce243a0214 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts @@ -0,0 +1,14 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* TODO b/217436680: remove the flash jedec-id override once the upstream + * change lands. + */ +&spi_fiu0 { + int_flash: w25q40@0 { + compatible ="jedec,spi-nor"; + jedec-id = [ef 40 14]; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts index 0adac68a8e..62268477f1 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts @@ -34,11 +34,13 @@ vol_dn_ec { gpios = <&gpio0 3 (GPIO_INPUT | GPIO_PULL_UP)>; }; - smc_lid { - gpios = <&gpio0 1 (GPIO_INPUT | GPIO_PULL_UP)>; + smc_lid: smc_lid { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_LID_OPEN"; }; - mech_pwr_btn_odl { + mech_pwr_btn_odl: mech_pwr_btn_odl { gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; }; std_adp_prsnt { gpios = <&gpio0 2 GPIO_INPUT>; @@ -114,12 +116,14 @@ }; ec_flash_wp_odl { gpios = <&gpio9 4 GPIO_INPUT>; + enum-name = "GPIO_WP_L"; }; ec_h1_packet_mode { gpios = <&gpioe 2 GPIO_OUT_LOW>; }; ec_entering_rw { gpios = <&gpiod 4 GPIO_OUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; }; ccd_mode_odl { gpios = <&gpiof 4 GPIO_INPUT>; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts new file mode 100644 index 0000000000..29cba96a29 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts @@ -0,0 +1,20 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/ { + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_lid_open: lid_open { + irq-pin = <&smc_lid>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_power_button: power_button { + irq-pin = <&mech_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf new file mode 100644 index 0000000000..273e983689 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf @@ -0,0 +1,8 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_ADLRVP_NPCX=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_SYSCON=y diff --git a/zephyr/projects/intelrvp/adlrvp/prj.conf b/zephyr/projects/intelrvp/adlrvp/prj.conf new file mode 100644 index 0000000000..eafdd1793b --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/prj.conf @@ -0,0 +1,3 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. diff --git a/zephyr/projects/intelrvp/include/gpio_map.h b/zephyr/projects/intelrvp/include/gpio_map.h new file mode 100644 index 0000000000..ac31d03926 --- /dev/null +++ b/zephyr/projects/intelrvp/include/gpio_map.h @@ -0,0 +1,9 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __ZEPHYR_GPIO_MAP_H +#define __ZEPHYR_GPIO_MAP_H + +#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/intelrvp/prj.conf b/zephyr/projects/intelrvp/prj.conf new file mode 100644 index 0000000000..2a593e8a15 --- /dev/null +++ b/zephyr/projects/intelrvp/prj.conf @@ -0,0 +1,21 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + + +CONFIG_CROS_EC=y +CONFIG_LTO=y +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_BRINGUP=y +CONFIG_PLATFORM_EC_POWER_BUTTON=y +CONFIG_PLATFORM_EC_LID_SWITCH=y +CONFIG_SHIMMED_TASKS=y + +# TODO +# Below conf are disabled to compile successfully +# These will be enabled in upcoming CLs +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n +CONFIG_PLATFORM_EC_I2C=n +CONFIG_PLATFORM_EC_KEYBOARD=n +CONFIG_PLATFORM_EC_VBOOT_EFS2=n +CONFIG_PLATFORM_EC_VBOOT_HASH=n |