diff options
Diffstat (limited to 'zephyr/shim/chip/npcx/include')
| -rw-r--r-- | zephyr/shim/chip/npcx/include/clock_chip.h | 14 | ||||
| -rw-r--r-- | zephyr/shim/chip/npcx/include/flash_chip.h | 31 | ||||
| -rw-r--r-- | zephyr/shim/chip/npcx/include/rom_chip.h | 57 | ||||
| -rw-r--r-- | zephyr/shim/chip/npcx/include/system_chip.h | 80 |
4 files changed, 0 insertions, 182 deletions
diff --git a/zephyr/shim/chip/npcx/include/clock_chip.h b/zephyr/shim/chip/npcx/include/clock_chip.h deleted file mode 100644 index 0c39ed8174..0000000000 --- a/zephyr/shim/chip/npcx/include/clock_chip.h +++ /dev/null @@ -1,14 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CLOCK_CHIP_H -#define __CROS_EC_CLOCK_CHIP_H - -/** - * TODO(b:180112248) implement in zephyr's clock_control.h - */ -void clock_turbo(void); - -#endif /* __CROS_EC_CLOCK_CHIP_H */ diff --git a/zephyr/shim/chip/npcx/include/flash_chip.h b/zephyr/shim/chip/npcx/include/flash_chip.h deleted file mode 100644 index 622633c570..0000000000 --- a/zephyr/shim/chip/npcx/include/flash_chip.h +++ /dev/null @@ -1,31 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_FLASH_CHIP_H -#define __CROS_EC_FLASH_CHIP_H - -#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ -#ifdef CONFIG_FLASH_SIZE -#define CONFIG_FLASH_SIZE_BYTES (CONFIG_FLASH_SIZE * 1024) -#else -#define CONFIG_FLASH_SIZE_BYTES 0x0 -#endif - -/* TODO(b:176490413): use DT_PROP(DT_INST(inst, DT_DRV_COMPAT), size) ? */ -#define CONFIG_MAPPED_STORAGE_BASE 0x64000000 -#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ -#define CONFIG_FLASH_ERASE_SIZE 0x10000 -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE - -/* RO image resides at start of protected region, right after header */ -#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE - -#define CONFIG_RW_STORAGE_OFF 0 - -/* Use 4k sector erase for NPCX monitor flash erase operations. */ -#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000 - -#endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/zephyr/shim/chip/npcx/include/rom_chip.h b/zephyr/shim/chip/npcx/include/rom_chip.h deleted file mode 100644 index aab166e6f1..0000000000 --- a/zephyr/shim/chip/npcx/include/rom_chip.h +++ /dev/null @@ -1,57 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_ROM_CHIP_H -#define __CROS_EC_ROM_CHIP_H - -#include "common.h" - -/* Enumerations of ROM api functions */ -enum API_SIGN_OPTIONS_T { - SIGN_NO_CHECK = 0, - SIGN_CRC_CHECK = 1, -}; - -enum API_RETURN_STATUS_T { - /* Successful download */ - API_RET_STATUS_OK = 0, - /* Address is outside of flash or not 4 bytes aligned. */ - API_RET_STATUS_INVALID_SRC_ADDR = 1, - /* Address is outside of RAM or not 4 bytes aligned. */ - API_RET_STATUS_INVALID_DST_ADDR = 2, - /* Size is 0 or not 4 bytes aligned. */ - API_RET_STATUS_INVALID_SIZE = 3, - /* Flash Address + Size is out of flash. */ - API_RET_STATUS_INVALID_SIZE_OUT_OF_FLASH = 4, - /* RAM Address + Size is out of RAM. */ - API_RET_STATUS_INVALID_SIZE_OUT_OF_RAM = 5, - /* Wrong sign option. */ - API_RET_STATUS_INVALID_SIGN = 6, - /* Error during Code copy. */ - API_RET_STATUS_COPY_FAILED = 7, - /* Execution Address is outside of RAM */ - API_RET_STATUS_INVALID_EXE_ADDR = 8, - /* Bad CRC value */ - API_RET_STATUS_INVALID_SIGNATURE = 9, -}; - -/* Macro functions of ROM api functions */ -#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40) -#define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \ - status) \ - (((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \ - (src_offset, dest_addr, size, sign, exe_addr, status)) - -/* Declarations of ROM api functions */ -typedef void (*download_from_flash_ptr) ( - uint32_t src_offset, /* The offset of the data to be downloaded */ - uint32_t dest_addr, /* The address of the downloaded data in the RAM*/ - uint32_t size, /* Number of bytes to download */ - enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */ - uint32_t exe_addr, /* jump to this address after download if not zero */ - enum API_RETURN_STATUS_T *status /* Status fo download */ -); - -#endif /* __CROS_EC_ROM_CHIP_H */ diff --git a/zephyr/shim/chip/npcx/include/system_chip.h b/zephyr/shim/chip/npcx/include/system_chip.h deleted file mode 100644 index c77c2a8338..0000000000 --- a/zephyr/shim/chip/npcx/include/system_chip.h +++ /dev/null @@ -1,80 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_SYSTEM_CHIP_H_ -#define __CROS_EC_SYSTEM_CHIP_H_ - -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) - -/* TODO(b:179900857) Clean this up too */ -#undef IS_BIT_SET -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) - -/*****************************************************************************/ -/* Memory mapping */ -#define CONFIG_LPRAM_BASE 0x40001400 /* memory address of lpwr ram */ -#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ - -/******************************************************************************/ -/* Optional M4 Registers */ -#define CPU_MPU_CTRL REG32(0xE000ED94) -#define CPU_MPU_RNR REG32(0xE000ED98) -#define CPU_MPU_RBAR REG32(0xE000ED9C) -#define CPU_MPU_RASR REG32(0xE000EDA0) - -/* - * Region assignment. 7 as the highest, a higher index has a higher priority. - * For example, using 7 for .iram.text allows us to mark entire RAM XN except - * .iram.text, which is used for hibernation. - * Region assignment is currently wasteful and can be changed if more - * regions are needed in the future. For example, a second region may not - * be necessary for all types, and REGION_CODE_RAM / REGION_STORAGE can be - * made mutually exclusive. - */ -enum mpu_region { - REGION_DATA_RAM = 0, /* For internal data RAM */ - REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ - REGION_CODE_RAM = 2, /* For internal code RAM */ - REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ - REGION_STORAGE = 4, /* For mapped internal storage */ - REGION_STORAGE2 = 5, /* Second region for unaligned size */ - REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ - REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ - /* only for chips with MPU supporting 16 regions */ - REGION_UNCACHED_RAM = 8, /* For uncached data RAM */ - REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */ - REGION_ROLLBACK = 10, /* For rollback */ -}; - -/* - * Configure the specific memory addresses in the the MPU - * (Memory Protection Unit) for Nuvoton different chip series. - */ -void system_mpu_config(void); - -/* The utilities and variables depend on npcx chip family */ -#if defined(CONFIG_SOC_SERIES_NPCX5) || \ - defined(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API) -/* Bypass for GMDA issue of ROM api utilities only on npcx5 series or if - * CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API is defined. - */ -void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t exeAddr); - -/* Begin address for hibernate utility; defined in linker script */ -extern unsigned int __flash_lpfw_start; - -/* End address for hibernate utility; defined in linker script */ -extern unsigned int __flash_lpfw_end; - -/* Begin address for little FW; defined in linker script */ -extern unsigned int __flash_lplfw_start; - -/* End address for little FW; defined in linker script */ -extern unsigned int __flash_lplfw_end; -#endif - -#endif // __CROS_EC_SYSTEM_CHIP_H_ |