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-rw-r--r--zephyr/test/ap_power/boards/alderlake.dts269
1 files changed, 0 insertions, 269 deletions
diff --git a/zephyr/test/ap_power/boards/alderlake.dts b/zephyr/test/ap_power/boards/alderlake.dts
deleted file mode 100644
index 30432a9c72..0000000000
--- a/zephyr/test/ap_power/boards/alderlake.dts
+++ /dev/null
@@ -1,269 +0,0 @@
-/* Copyright 2022 The ChromiumOS Authors
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <dt-bindings/gpio_defines.h>
-
-/ {
- common-pwrseq {
- compatible = "intel,ap-pwrseq";
- s5-inactivity-timeout = <1>;
- };
-
- en_pp5000: pwr-en-pp5000-s5 {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "PP5000_S5 enable output to regulator";
- enum-name = "PWR_EN_PP5000_A";
- gpios = <&gpio0 10 0>;
- output;
- };
- en_pp3300: pwr-en-pp3300-s5 {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "PP3300_S5 enable output to LS";
- enum-name = "PWR_EN_PP3300_A";
- gpios = <&gpio0 11 0>;
- output;
- };
- rsmrst: pwr-pg-ec-rsmrst-odl {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "RSMRST power good from regulator";
- enum-name = "PWR_RSMRST";
- gpios = <&gpio0 12 0>;
- interrupt-flags = <GPIO_INT_EDGE_BOTH>;
- };
- ec_pch_rsmrst: pwr-ec-pch-rsmrst-odl {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "RSMRST output to PCH";
- enum-name = "PWR_EC_PCH_RSMRST";
- gpios = <&gpio0 13 0>;
- output;
- };
- slp_s0: pwr-slp-s0-l {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "SLP_S0_L input from PCH";
- enum-name = "PWR_SLP_S0";
- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
- interrupt-flags = <GPIO_INT_EDGE_BOTH>;
- no-enable;
- };
- slp_s3: pwr-slp-s3-l {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "SLP_S3_L input from PCH";
- enum-name = "PWR_SLP_S3";
- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
- interrupt-flags = <GPIO_INT_EDGE_BOTH>;
- };
- slp_sus: pwr-slp-sus-l {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "SLP_SUS_L input from PCH";
- enum-name = "PWR_SLP_SUS";
- gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
- interrupt-flags = <GPIO_INT_EDGE_BOTH>;
- };
- ec_soc_dsw_pwrok: pwr-ec-soc-dsw-pwrok {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "DSW_PWROK output to PCH";
- enum-name = "PWR_EC_SOC_DSW_PWROK";
- gpios = <&gpio0 17 0>;
- output;
- };
- pwr-vccst-pwrgd-od {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "VCCST_PWRGD output to PCH";
- enum-name = "PWR_VCCST_PWRGD";
- gpios = <&gpio0 18 0>;
- output;
- };
- pwr-imvp9-vrrdy-od {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "VRRDY input from IMVP9";
- enum-name = "PWR_IMVP9_VRRDY";
- gpios = <&gpio0 19 0>;
- };
- pch_pwrok: pwr-pch-pwrok {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "PCH_PWROK output to PCH";
- enum-name = "PWR_PCH_PWROK";
- gpios = <&gpio0 20 0>;
- output;
- };
- pwr-ec-pch-sys-pwrok {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "SYS_PWROK output to PCH";
- enum-name = "PWR_EC_PCH_SYS_PWROK";
- gpios = <&gpio0 21 0>;
- output;
- };
- pwr-sys-rst-l {
- compatible = "intel,ap-pwrseq-gpio";
- dbg-label = "SYS_RESET# output to PCH";
- enum-name = "PWR_SYS_RST";
- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
- output;
- };
- slp_s4: pwr-slp-s4 {
- compatible = "intel,ap-pwrseq-vw";
- dbg-label = "SLP_S4 virtual wire input from PCH";
- enum-name = "PWR_SLP_S4";
- virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
- vw-invert;
- };
- slp_s5: pwr-slp-s5 {
- compatible = "intel,ap-pwrseq-vw";
- dbg-label = "SLP_S5 virtual wire input from PCH";
- enum-name = "PWR_SLP_S5";
- virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
- vw-invert;
- };
- all_sys_pwrgd: pwr-all-sys-pwrgd {
- compatible = "intel,ap-pwrseq-external";
- dbg-label = "Combined all power good";
- enum-name = "PWR_ALL_SYS_PWRGD";
- };
- dsw_pwrok: pwr-pp3300-pwrok {
- compatible = "intel,ap-pwrseq-external";
- dbg-label = "PP3300 PWROK";
- enum-name = "PWR_DSW_PWROK";
- };
- pwr-pp1p05-pwrok {
- compatible = "intel,ap-pwrseq-external";
- dbg-label = "PP1P05 PWROK";
- enum-name = "PWR_PG_PP1P05";
- };
-
- en_pp3300_emul: en-pp3300-emul {
- compatible = "intel,ap-pwr-signal-emul";
- input-signal = <&en_pp3300>;
- init-value = <0>;
- pp3300-dsw-pwrok-emul {
- output-signal = <&dsw_pwrok>;
- assert-delay-ms = <10>;
- init-value= <0>;
- };
- };
-
- en_pp5000_emul: en-pp5000-emul {
- compatible = "intel,ap-pwr-signal-emul";
- input-signal = <&en_pp5000>;
- init-value = <0>;
- pp5000-rsmrst-emul {
- output-signal = <&rsmrst>;
- assert-delay-ms = <40>;
- init-value= <0>;
- };
- };
-
- ec_soc_dsw_pwrok_emul: ec-soc-dsw-pwrok-emul {
- compatible = "intel,ap-pwr-signal-emul";
- input-signal = <&ec_soc_dsw_pwrok>;
- init-value = <0>;
- ec-dsw-pwrok-slp-sus-emul {
- output-signal = <&slp_sus>;
- assert-delay-ms = <20>;
- init-value= <0>;
- };
- };
-
- ec_pch_rsmrst_emul: ec-pch-rsmrst-emul {
- compatible = "intel,ap-pwr-signal-emul";
- input-signal = <&ec_pch_rsmrst>;
- init-value = <0>;
- ec-pch-rsmrst-slp-s5-emul {
- output-signal = <&slp_s5>;
- assert-delay-ms = <20>;
- invert-value;
- init-value= <1>;
- };
- ec-pch-rsmrst-slp-s4-emul {
- output-signal = <&slp_s4>;
- assert-delay-ms = <30>;
- invert-value;
- init-value= <1>;
- };
- ec-pch-rsmrst-slp-s3-emul {
- output-signal = <&slp_s3>;
- assert-delay-ms = <40>;
- init-value= <0>;
- };
- ec-pch-rsmrst-slp-s0-emul {
- output-signal = <&slp_s0>;
- assert-delay-ms = <45>;
- init-value= <0>;
- };
- ec-pch-rsmrst-all-sys-pwrgd {
- output-signal = <&all_sys_pwrgd>;
- assert-delay-ms = <50>;
- init-value= <0>;
- };
- };
-
- tp-sys-g3-to-s0 {
- compatible = "intel,ap-pwr-test-platform";
- nodes = <&en_pp3300_emul &en_pp5000_emul
- &ec_soc_dsw_pwrok_emul &ec_pch_rsmrst_emul>;
- };
-
- pch_pwrok_power_fail_emul: pch-pwrok-power-fail-emul {
- compatible = "intel,ap-pwr-signal-emul";
- input-signal = <&pch_pwrok>;
- init-value = <0>;
- pch-pwrok-dsw-pwrok-emul {
- output-signal = <&dsw_pwrok>;
- assert-delay-ms = <50>;
- invert-value;
- };
- };
-
- tp-sys-s0-power-fail {
- compatible = "intel,ap-pwr-test-platform";
- nodes = <&pch_pwrok_power_fail_emul>;
- };
-
- pch_pwrok_power_down_emul: pch-pwrok-power-down-emul {
- compatible = "intel,ap-pwr-signal-emul";
- input-signal = <&pch_pwrok>;
- init-value = <0>;
- edge = "EDGE_ACTIVE_ON_ASSERT";
- pch-pwrok-dsw-pwrok-emul {
- output-signal = <&dsw_pwrok>;
- assert-delay-ms = <70>;
- invert-value;
- };
-
- pch_pwrok-rsmrst-emul {
- output-signal = <&rsmrst>;
- assert-delay-ms = <60>;
- invert-value;
- };
-
- pch-pwrok-slp-s5-emul {
- output-signal = <&slp_s5>;
- assert-delay-ms = <50>;
- };
-
- pch-pwrok-slp-s4-emul {
- output-signal = <&slp_s4>;
- assert-delay-ms = <30>;
- };
-
- pch-pwrok-slp-s3-emul {
- output-signal = <&slp_s3>;
- assert-delay-ms = <20>;
- invert-value;
- };
-
- pch-pwrok-slp-s0-emul {
- output-signal = <&slp_s0>;
- assert-delay-ms = <15>;
- invert-value;
- };
- };
-
- tp-sys-g3-to-s0-power-down {
- compatible = "intel,ap-pwr-test-platform";
- nodes = <&en_pp3300_emul &en_pp5000_emul
- &ec_soc_dsw_pwrok_emul &ec_pch_rsmrst_emul
- &pch_pwrok_power_down_emul>;
- };
-};