diff options
Diffstat (limited to 'zephyr/test/ap_power/boards/native_posix.overlay')
| -rw-r--r-- | zephyr/test/ap_power/boards/native_posix.overlay | 196 |
1 files changed, 196 insertions, 0 deletions
diff --git a/zephyr/test/ap_power/boards/native_posix.overlay b/zephyr/test/ap_power/boards/native_posix.overlay new file mode 100644 index 0000000000..c6cd8c3790 --- /dev/null +++ b/zephyr/test/ap_power/boards/native_posix.overlay @@ -0,0 +1,196 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <board-overlays/native_posix.dts> +#include <cros/binman.dtsi> +#include <dt-bindings/gpio_defines.h> +#include <freq.h> + +/ { + chosen { + cros-ec,espi = &espi0; + intel-ap-pwrseq,espi = &espi0; + }; + + /* + * Keep these GPIOs in pin order. + * If you need to add one, make sure you increase + * ngpios in the gpio0 node further down. + */ + named-gpios { + compatible = "named-gpios"; + + gpio_ec_pwr_btn_odl: ec_pwr_btn_odl { + /* GPIO_PULL_UP will cause this start asserted, + * i.e. not pressed. + */ + gpios = <&gpio0 1 (GPIO_INPUT | GPIO_PULL_UP)>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_pch_pwrbtn_l: pch_pwrbtn_l { + gpios = <&gpio0 2 GPIO_OUTPUT>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpio0 3 GPIO_OUTPUT_HIGH>; + }; + gpio_lid_open_ec: lid_open_ec { + /* GPIO_PULL_UP will cause this start asserted. */ + gpios = <&gpio0 4 (GPIO_INPUT | GPIO_PULL_UP)>; + enum-name = "GPIO_LID_OPEN"; + }; + }; + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_lid_open_ec: lid_open_ec { + irq-pin = <&gpio_lid_open_ec>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio0 10 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpio0 11 0>; + output; + }; + pwr-pg-ec-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio0 12 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpio0 13 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + no-enable; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio0 17 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpio0 18 0>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio0 19 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio0 20 0>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio0 21 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-pp3300-pwrok { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "PP3300 PWROK"; + enum-name = "PWR_DSW_PWROK"; + }; + pwr-pp1p05-pwrok { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "PP1P05 PWROK"; + enum-name = "PWR_PG_PP1P05"; + }; + + clock: clock { + compatible = "cros,clock-control-emul"; + clock-frequency = <DT_FREQ_M(100)>; /* 100 MHz */ + }; +}; + +&espi0 { + espi-host@0 { + status = "okay"; + compatible = "zephyr,espi-emul-espi-host"; + reg = <0x0>; + }; +}; + +&gpio0 { + ngpios = <23>; +}; |