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* uart_buffer: ensure uart tx/rx buffer size are power of twoYilun Lin2019-11-071-1/+4
| | | | | | | | | | | | | | | | uart buffers are circular buffers and the pointer advancing needs the buffer size power of two. TEST=set CONFIG_UART_TX/RX_BUF_SIZE to various values and ensure the results are correct BUG=none BRANCH=kukui Change-Id: I53feb28f0397c67e282126faf25b0fbfdd8d5251 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902889 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* chip/stm32: Fix compile with gcc8Patrick Georgi2019-11-071-2/+2
| | | | | | | | | | | | | | | | | gcc8 packs uint8 arrays more tightly sometimes, which is bad if a device expects a certain alignment, so make the 4byte alignment of gcc 4.9 explicit for the buffers. BUG=b:132204142 TEST=sweetberry firmware built with coreboot-sdk reaches the console Change-Id: I24cf151d2df21e106fbb7e8f5b16a3bab81b09ab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1899437 Tested-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Brian Nemec <bnemec@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* usb_pd_protocol: disable vconn on pd_suspendCaveh Jalali2019-11-071-0/+3
| | | | | | | | | | | | | this disables VCONN on a port before we start the TCPC firmware update. BUG=b:143330980 BRANCH=none TEST=tested TCPC firmware update on atlas Change-Id: I2b0b8d52d637acf5b7adfdc37ef4ae4871054f5b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1899077 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Kindred: support factory keyboard test.ben.chen2@quanta.corp-partner.google.com2019-11-072-1/+23
| | | | | | | | | | | | | | | | | | | | | | connector-to-GPIO map: {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, BUG=b:143927624 BRANCH=master TEST=`ectool kbfactorytest` PASS. Change-Id: I67b8ebd1edb238a265bd6f9e5e98100b5635a2d6 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898256 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* kukui: Support mt6370 bc12 detect apple/samsung TATJ Wu2019-11-072-42/+190
| | | | | | | | | | | | | | | | Support mt6370 bc12 detect apple/samsung TA TEST=plug in apple/samsung TA, and use power supply check charger type BUG=b:118791032 b:122866184 BRANCH=kukui Change-Id: Ieb684f7a3d38e3b36aab9bcf27cbc823b5a7df81 Signed-off-by: TJ Wu <tj_wu@richtek.com> Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1351910 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org>
* puff: Complete GPIO list for EC.Andrew McRae2019-11-073-44/+148
| | | | | | | | | | | | | | | | | Fill out the GPIO entries for puff. Some dependencies on the hatch power sequencing still exist, and will need to be modified for the puff power handling. BRANCH=none BUG=b:143189339 TEST=Build image, buildall, tests Change-Id: I60074298be3d75e447c32ee3448f67149ec1bf81 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898261 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* puff: Add fan configuration to EC.Andrew McRae2019-11-072-10/+11
| | | | | | | | | | | | | | | Add fan configuration to puff. BRANCH=none BUG=b:143327224 TEST=Build puff, tests, buildall. Change-Id: Ib968dafa297c7d17ea0d90c0b67869f5aca5e210 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1899653 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* Revert "usbc: remove unnecessary tcpc CC reads"Sam Hurst2019-11-064-203/+463
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bec03d91bc9f954682c02d122a0500d10cc102c2. Reason for revert: Some TCPC's bugs will generate an attach event when nothing is connected, triggering the state machine to enter an attached state. Example output with nothing connected to the port: 2019-10-28 10:23:20 [0.044393 C1: Unattached.SNK] 2019-10-28 10:23:20 [0.101264 p1: PPC init'd.] 2019-10-28 10:23:20 [0.106488 C1: Unattached.SRC] 2019-10-28 10:23:20 [0.116072 C1: AttachWait.SRC] 2019-10-28 10:23:20 [0.220006 C1: Attached.SRC] TOT has basic TypeC/PD functionality but issues still exist that will be fixed in subsequent CLs. Original change's description: > usbc: remove unnecessary tcpc CC reads > > We only need to read the CC pins when the CC evt is fired otherwise the > CC pins should have the same value. It is actually incorrect/undesirable > that our old PD stack queried the tpcp cc driver over i2c so frequently > for the CC pins status. > > Also single source code that interprets the CC lines values into a UFP > or DFP state. > > Lastly, remove extraneous timers for cc debouncing, we only need one. > > BRANCH=none > BUG=none > TEST=builds > > Change-Id: I65baa2e6fb92d7ab5ca12daa76225cd13b9ab974 > Signed-off-by: Jett Rink <jettrink@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1825504 > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Reviewed-by: Sam Hurst <shurst@google.com> > Commit-Queue: Denis Brockus <dbrockus@chromium.org> Bug: none Change-Id: Ie9bd366dd85df9a33934e06e4208543f6e7aaa9b Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1900058 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* nocturne_fp/hatch_fp: Document alternate namesTom Hughes2019-11-062-2/+17
| | | | | | | | | | | | | | | There are many variations of "board" names for the FPMCU, but they all refer to one of two hardware configurations. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I5c57fab1976f2aea395d8319c4f9c52f8134129a Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894454 Reviewed-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* servo_v4: Use the correct voltage threshold on the flipped CC directionWai-Hong Tam2019-11-061-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the DTS mode, servo pulls up CC lines with different Rp values. When detecting DUT Rd value, servo senses the CC voltage values, and checks it using some table of voltage thresholds. The tables assume CC1 is the primary CC and CC2 is the alternative CC. When servo emulates the flipped CC scenario, should use the correct colume to check the voltage thresholds. BRANCH=servo BUG=b:136014621, b:140876537 TEST=Configed servo to emulate the flipped scenario in dts mode: > cc srcdts cc2 Verified it detect the correct Rd values in DUT (CC0 and CC1 are 2, i.e. TYPEC_CC_VOLT_RD): > tcpc 1 state Port C1, Ena - CC:1, CC0:2, CC1:2 Alert: 0x00 Mask: 0x007d Power Status: 0x48 Mask: 0x00 Without this patch, it detected wrong Rd values in DUT (CC0 is 2, i.e. TYPEC_CC_VOLT_RD, but CC1 is 0, i.e. TYPEC_CC_VOLT_OPEN): > tcpc 1 state Port C1, Ena - CC:1, CC0:2, CC1:0 Alert: 0x00 Mask: 0x007d Power Status: 0x48 Mask: 0x00 Change-Id: Iaf089356230f24f871636956780cb5652fec5c42 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1876800 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* docs: update link to host commands documentationHarry Cutts2019-11-061-1/+1
| | | | | | | | | | | | | | The Google Sites version was deprecated when https://crrev.com/c/1807964 was submitted. BRANCH=none BUG=none TEST=Check the rendering in Gitiles Change-Id: I440ae76501a4eb747e4a2e4550c192565c3c6717 Signed-off-by: Harry Cutts <hcutts@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1900666 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* dratini: enable keyboard factory scanningDevin Lu2019-11-062-0/+24
| | | | | | | | | | | | | | | | Clone from CL:1309572 This patch add for factory keyboard connector test. BUG=none BRANCH=none TEST=Short keyboard pins and make sure "ectool kbfactorytest" works. Change-Id: I06deb1539845bc3490c69943579aa4b6bbc1d4ab Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898258 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* dratini: remove unused ALS sensor idDevin Lu2019-11-061-3/+1
| | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j. Change-Id: I4cf3d353afaaf4d422421b1a35c137f74259f962 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898248 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* hatch_fp/nocturne_fp: Disable CONFIG_SYSTEM_UNLOCKED by defaultTom Hughes2019-11-062-6/+2
| | | | | | | | | | | | | | | | The release branch disables CONFIG_SYSTEM_UNLOCKED, but to prevent confusion (and potential mistakes), we will just always disable CONFIG_SYSTEM_UNLOCKED since the write protection scheme for fingerprint is final. BRANCH=none BUG=b:130249462,b:73337313 TEST=make buildall -j Change-Id: I072a5e037d80fbde39a5b695da7b2bd6de64e04c Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1895605 Reviewed-by: Yicheng Li <yichengli@chromium.org>
* touchpad_gt7288: replace Kernel-doc with DoxygenHarry Cutts2019-11-062-30/+35
| | | | | | | | | | | | | | | | When I wrote the driver I was under the mistaken impression that Kernel-doc style documentation comments were in use it CrOS EC. Looking at it now, Doxygen is far more common. BUG=chromium:991365 TEST=make buildall -j BRANCH=none Change-Id: I25be469d362bba256fdfb7f81438da28f24bfeb5 Signed-off-by: Harry Cutts <hcutts@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1899337 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Craig Hesling <hesling@chromium.org>
* Aleena: support factory keyboard test.David Huang2019-11-052-0/+27
| | | | | | | | | | | | | | | | | | | | | | connector-to-GPIO map: {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},{2, 2}, {3, 0}, {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, {-1, -1}, BUG=b:143848117 BRANCH=master TEST="ectool kbfactorytest" Pass. Change-Id: I087c4f11338e58d20ad82ce94c4c64380945c56f Signed-off-by: David Huang <David.Huang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893909 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: David Huang <david.huang@quanta.corp-partner.google.com> Tested-by: David Huang <david.huang@quanta.corp-partner.google.com>
* Kodama: battery discharge power to system when battery charged to 4.1v at 45 ↵xiong.huang2019-11-051-0/+10
| | | | | | | | | | | | | | | | | | | deg C After battery charged to 4.1V at 45 deg C, the desired voltage of the smart battery is still 4.4V, and battery will discharge power to system. When smart battery temperature is more than 45 deg C, the max charging voltage for battery is set as 4.1V. BUG=b:142669003 BRANCH=kukui TEST=Verified on four DUTs in 45 deg C and passed. Change-Id: I2c2b0d43ed29b33beb37ba4d75ecb653f156c9a7 Signed-off-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880774 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* usb_pd_protocol: ignore PD resume on enabled portCaveh Jalali2019-11-051-14/+18
| | | | | | | | | | | | | | | | | | | | the easiest way to test this is to do multiple "ectool pdcontrol resume 1" on the AP with a dummy load like a USB flashlight inserted into the port. previously, doing a resume on an operational port would confuse the PD state machine and end up in a SNK_DISCONNECT <-> SNK_DISCONNECT_DEBOUNCE loop. now, it does nothing. however, "ectool pdcontrol suspend 1" follwed by "ectool pdcontrol resume 1" brings the port down, then brings it back up as expected. BUG=b:143330980 BRANCH=none TEST=run multiple "ectool pdcontrol resume 1" commands on AP Change-Id: Iea5daaf36c8f299c1cb8443fb6892b00c845c517 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1890776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* treeya: fix rotation matrix of kx022 lid sensorLu Zhang2019-11-051-1/+0
| | | | | | | | | | | | | | | | The layout has been changed. Need to follow the HW changes. BUG=b:143848116 BRANCH=none TEST=Using ec console 'accelinfo on' verified lid angle now goes from 0 to 360 and swtiches to tablet mode after crossing 180 threshold. Signed-off-by: Lu Zhang <lu.zhang@bitland.corp-partner.google.com> Change-Id: I3ad16a44b419bcce38f0cdbf8d74e6b4876c7250 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1886590 Tested-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* host: adding gpio print for debuggingJett Rink2019-11-041-0/+12
| | | | | | | | | | | | | | | Add console print when GPIO line changes for easier unit test debugging BRANCH=none BUG=none TEST=verified that gpio print occurs in unit tests Change-Id: I888859c8ef4a1b879146e9c01767ee487f7ce564 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1896124 Commit-Queue: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Raul E Rangel <rrangel@chromium.org>
* Kodama: Modify celxpert battery parameterxiong.huang2019-11-041-2/+2
| | | | | | | | | | | | | | Base on celxpert battery SPEC, pre-charge current is 404mA and over discharge voltage is 2.8V. BUG=b:138826367 TEST=Base on celxpert battery SPEC. BRANCH=kukui Change-Id: I7714e2392f9de3190964f25980871ab78c2ad309 Signed-off-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893900 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* kukui_scp: Enable CONFIG_HOSTCMD_ALIGNEDYilun Lin2019-11-041-0/+2
| | | | | | | | | | | | | | | To have more efficient HC structure. The usage of SRAM only increase by 21 bytes. TEST=make BOARD=kukui_scp BUG=b:136979732 BRANCH=kukui Change-Id: I86dd582faceff9651320e566d916e68e47f0cb83 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893902 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* puff: populate ADCs and temperature sensorsPeter Marheine2019-11-042-20/+90
| | | | | | | | | | | | | | Several analog channels are needed for power sequencing, and may as well fill them all in while we're here. BUG=b:143188569 TEST=image builds and links BRANCH=None Change-Id: I99c2def362b11bef0748adfe11cc7356bb1591c6 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893016 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* ec-fans: Make fans configuration const by default.Andrew McRae2019-11-0219-15/+26
| | | | | | | | | | | | | | | | It was pointed out to me that the fans config list was non-const, but there is only 2 boards that require non-const configuration, so by default make it const, but allow an override. BRANCH=none BUG=None TEST=EC compiles, make tests, buildall Change-Id: I3ef8c72f6774e1a76584c47d89287f446199e0f2 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893025 Reviewed-by: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* mt_scp/gpio: set GPIO_ALT_FUNC_NONE to GPIO_ALT_FUNC_DEFAULTYilun Lin2019-11-021-1/+3
| | | | | | | | | | | | | | | | The common EC code expects that if the func parameter passed to gpio_set_alternate_function() is -1 (GPIO_ALT_FUNC_NONE), that the pin will be reassigned to a GPIO function. TEST=make buildall BUG=b:143710991 BRANCH=kukui Change-Id: I6ba3d3d323e4fb99617ce4baaec662ceab094ad4 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893026 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Revert "usbc: update CRCReceiveTimer"Sam Hurst2019-11-022-17/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1092c786f7876745ec0d68dd52284d252e1abee5. Reason for revert: <Several Fluffy tests failed due to this CL> Original change's description: > usbc: update CRCReceiveTimer > > Shorten the CRCReceiveTimer and document that either the pe send or > error function will get called in response to a prl_ send message. > > BRANCH=none > BUG=none > TEST=build; > > Change-Id: Icc43886cadfdcd67c943b25aebfdfb55b2693ade > Signed-off-by: Jett Rink <jettrink@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1825514 > Tested-by: Denis Brockus <dbrockus@chromium.org> > Commit-Queue: Denis Brockus <dbrockus@chromium.org> > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Reviewed-by: Edward Hill <ecgh@chromium.org> Bug: none Change-Id: I2051b6c2f3f36d5d0612f24ba08f9843f9487f66 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894765 Reviewed-by: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* servo_v4: The polarity is based on the flags in SRC DTS modeWai-Hong Tam2019-11-023-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the port in SRC DTS mode, it should not perform the polarity detection. The polarity is predetermined, as a board-specific setting. In the servo case, the polarity is based on the flags. This CL changes the protocol layer to check the port in SRC DTS mode and call the board-specific function board_get_src_dts_polarity() for the polarity. BRANCH=servo BUG=b:140876537 TEST=Configed servo as srcdts and unflipped direction: > cc srcdts cc2 Verified the power negotiation good and detected the correct polarity: > pd 1 state Port C1 CC2, Ena - Role: SRC-UFP State: SRC_READY, Flags: 0x415e Without this patch, it detected the wrong polarity and the power negotiation failed: > pd 1 state Port C1 CC1, Ena - Role: SRC-DFP State: SRC_DISCOVERY, Flags: 0x10608 Change-Id: I32c5dfffeaeb20a21db1417f3a1c98566b7f5e38 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1891255 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* max32660: add I2C board address support, refactorJerry Bradshaw2019-11-022-424/+287
| | | | | | | | | | | | | | | | | | | | | | Adds support for a second I2C slave address, modeled on the same feature in the STM32-F4. Also refactored the I2C slave interrupt handler to streamline host read and writes, reduced I2C slave state variable usage, and make better use of I2C slave interrupt types. BRANCH=none BUG=none TEST=Slave tested with EC CMDs and board cmds sent from a custom written EC HOST using another MAX32660 device as an I2C Master. Tested with Raspberry PI that emulates EC HOST and board commands. Change-Id: I575a283a9a6735b16f4b6ac0fcb0aa2d1984ee92 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1864791 Reviewed-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org> Tested-by: Harry Cutts <hcutts@chromium.org> Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* fmap: Remove CONFIG_RO_STORAGE_OFF from EC_RO offsetScott Collyer2019-11-011-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The value CONFIG_RO_STORAGE_OFF was being used to define the area_offset for EC_RO. This means that when flashing EC_RO from the DUT, the bootloader region is not being written. This is causing issues when doing RO updates (like in dogfood programs) as the full data section is not being loaded properly. In the case of npcx, the previous bootloader would be coupled with the new RO image, This CL removes CONFIG_RO_STORAGE_OFF from the area_offset field of EC_RO so that both the header and RO image are written. BUG=b:142907781 BRANCH=None TEST=Tested with a script that mimics auto update by writing an older version of FW to RO, then uses the DUT to flash just the RO with a new version and then compares the RO that was read to what was supposed to be written. This script would always fail before, but with this CL now passes multiple iterations. Change-Id: I3d7af7de0dc1dfd24d6d304a8271290e6c6eb94e Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1885107 Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Tested-by: Shelley Chen <shchen@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-01204-533/+549
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* kindred: Modify EC fan control tableben.chen2@quanta.corp-partner.google.com2019-11-011-7/+7
| | | | | | | | | | | | | | | | | | | | | Modify EC fan control table by Thermal request. BUG=b:136567378 BRANCH=Master TEST=Manual Verify fan behavior by thermal team. Remove DPTF and check fan speed with temperature. When temperature over 25 degree, the fan start working. When temperature over 55 degree, the fan full run. And check system shutdown when temperature over 75 degree. Change-Id: I1f91eea6e98e65bd93f62c33a52ff3d91558abc1 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1873862 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* juniper: add new battery for next juniper buildTing Shen2019-11-012-0/+28
| | | | | | | | | | | | | | BUG=b:143334368 TEST=1) See "[0.064610 found batt:PANASONIC]" on EC console 2) battery readings looks reasonable BRANCH=master Change-Id: I5a7091ea7db6ff3f524ac5bd99bc6a7d3bdcd181 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880771 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* puff: Scrub config and generate hardware structuresAndrew McRae2019-11-014-27/+157
| | | | | | | | | | | | | | | | | | Verify all CONFIG items in board/puff/board.h. Generate the necessary hardware reference structures in board.c Generate the minimum GPIO references in order to build cleanly. v2: Remove some of the fan and temp sensors config. BUG=b:143564865 TEST=Compile and link EC image. Change-Id: Ibc073718ad1c85705ab460d96202799f8c4fea06 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893013 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org>
* atlas: initialize max charge currentCaveh Jalali2019-11-011-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | the isl923x is strapped to initialize the charge current to 3A. however, its default max charge current limit is 3.072. when the charge current exceeds the current limit, the charger asserts PROCHOT which means the AP gets throttled to 400MHz until the charge_state machine updates the current limit. on an unlocked system, we don't change the charge limit from its default, so we never apply the 5% derating needed to avoid the isl923x from over-currenting the charger. the solution is to over-ride the 3A strapping of the isl923x by appling a 5% derated current request early when we boot up. BUG=b:141533503 BRANCH=none TEST=atlas no longer boots into PROCHOT on 5v3a charger Change-Id: Idba55edf7b1c0eec36b6583aa0b276c3cb1f0c89 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889312 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* volteer: Add manual power sequencingKeith Short2019-11-014-1/+220
| | | | | | | | | | | | | | | As backup if board driven power sequencing doesn't work, implement EC controlled power sequencing on Volteer. BUG=b:140556273 BRANCH=none TEST=make buildall TEST=make BOARD=volteer VOLTEER_POWER_SEQUENCE=y Change-Id: I62e30e5f153085e2e6c26005a77e2e1abe981b0a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881754 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* gpio: add function to set a GPIO and log to the consoleKeith Short2019-11-012-0/+19
| | | | | | | | | | | | | | Add a common function gpio_set_level_verbose() to generate a cprints() statement prior to changing the GPIO pin level. BUG=none BRANCH=none TEST=make buildall Change-Id: I6b3a9e89604fb721d8fa5208ce96df9e9414cdf9 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893633 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tigerlake/icelake: add support for SYS_PWROKKeith Short2019-11-015-20/+74
| | | | | | | | | | | | | | | | | Add code to pass through PG_EC_ALL_SYS_PWRGD from the platform to the PCH signal PCH_SYS_PWROK. These signals correspond to the Intel signal names ALL_SYS_PWRGD and PCH_SYS_PWROK, respectively. BUG=b:143373337 BRANCH=none TEST=make buildall -j Change-Id: Iff86508450a5bca8c97fb855fa1a3a586edd99ff Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881753 Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* atlas: fix charger selection messagesCaveh Jalali2019-11-011-2/+2
| | | | | | | | | | | | | | | this corrects the printed text and switches from CPRINTF to CPRINTS for time stamping. BRANCH=none BUG=none TEST=buildall passes Change-Id: I4647ef4348a44d3eb433afa96ad04f2483899bc0 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1886034 Commit-Queue: Sean Abraham <seanabraham@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tcpci: fix tcpc_alert error messageCaveh Jalali2019-11-011-2/+2
| | | | | | | | | | | | | | this adds a missing newline to the end of a CPRINTF format string. BRANCH=none BUG=none TEST=builall passes Change-Id: I4a380983bce107af7a0f6eb7304bb9090c5b621a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1886033 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* tglrvp: Correct GPIO alternate function parameterVijay Hiremath2019-11-011-11/+11
| | | | | | | | | | | | | | | | Modified the gpio.inc file to reflect the new changes done for the alternate function parameter. BUG=b:139427854 BRANCH=none TEST=make buildall -j Change-Id: I3eed1b825f390581975d44734b62b7a73a2acb98 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880975 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Cleanup: Correct GPIO alternate function parameterVijay Hiremath2019-11-0114-50/+95
| | | | | | | | | | | | | | | Added code to correct the GPIO alternate function parameter at Chipset level. Optionally board level functions can cleanup the code in additional change lists. BUG=b:139427854 BRANCH=none TEST=make buildall -j Change-Id: I1171ca36a703291070fc89f972f84414adcf04fc Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880974 Reviewed-by: Keith Short <keithshort@chromium.org>
* Cleanup: Renaming pd_is_ufp to pd_partner_is_ufpAyushee2019-11-014-7/+13
| | | | | | | | | | | | | | | | pd_is_ufp function returns port partner CC status, renaming it to pd_partner_is_ufp to avoid ambiguity between host and port partner's CC status. BUG=b:141971044 BRANCH=None TEST=make buildall -j Change-Id: I19da8c8470db134e438271b92918994d77e4eb5d Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894119 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* usbc: Get current DP pin mode and CC stateAyushee2019-11-016-18/+89
| | | | | | | | | | | | | | | | | | | | | | | | To configure Intel virtual mux and burnside bridge retimer, current DP pin mode, cc state and the type of the cable is required. Hence, implemented a board level function that returns the current DP pin mode and added a function that returns the type of cable inaccordance to the cable vdo response. Also added a new version to USB_PD_CONTROL host command, to return the DP mode, cc_state and the cable type BUG=b:141971044 BRANCH=None TEST=Verifed with ectool usbpd command on CPU console, able to get correct CC state, pin mode and cable type Pin mode: USB:0x0 (No DP) DP cable:0x4 (Mode:C) USBC dock:0x8 (Mode:D) Change-Id: If87ae6b77e5fa2ceaa22319dfa2d2c802460edfa Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1835030 Reviewed-by: Keith Short <keithshort@chromium.org>
* cometlake: cleanup power signal namesKeith Short2019-10-314-25/+26
| | | | | | | | | | | | | | | Add X86 prefix to the Comet Lake signals names for consistency with other Intel APs. BUG=none BRANCH=none TEST=make buildall Change-Id: I70b2a261fd6fbc0e6de70e5d4cf3a90b35078d4e Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1888596 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* docs: ccd_cr50 fix headingsMary Ruthven2019-10-311-18/+18
| | | | | | | | | | | BUG=none BRANCH=none TEST=view docs Change-Id: I68ba4ffcb09942fe80d6c0406bf946795114eb54 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894130 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Use actual utilities dependency, not phony targetStefan Reinauer2019-10-311-2/+2
| | | | | | | | | | | | | | | | | | | | | | This prevents the EC binaries unnecessarily being recreated every time you run make on the target. BUG=none TEST= make BOARD=scarlet [..] make BOARD=scarlet *** 11460 bytes in flash and 10252 bytes in RAM still available on scarlet RO **** *** 24140 bytes in flash and 10252 bytes in RAM still available on scarlet RW **** BRANCH=none Change-Id: I6cabb7d1b7512162c8b24c7664bafc7d98c5eda5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1851106 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com>
* drallion_ish: Remove CONFIG_GMR_TABLET_MODE_CUSTOM from drallion ishMathew King2019-10-312-6/+0
| | | | | | | | | | | | | | | | GMR_TABLET_MODE_CUSTOM is needed on arcada_ish due to a hall sensor which is too sensitive. Drallion should not have the same problem. BUG=b:140311300 TEST='emerge-drallion chromeos-ish' ec log shows tablet mode events BRANCH=none Change-Id: Idde16dafb52c3da51b111031ed5144f5c428d62e Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893185 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* cr50: Move 30 ms ec_rst delay to after falling edgeMathew King2019-10-311-15/+9
| | | | | | | | | | | | | | | Platfoms with closed EC require at least 30 ms to put the EC in reset. In order to support flashrom over CCD move this 30 ms delay from before the deassertion of EC reset to after assertion. BUG=b:142100741 TEST=Run flashrom over CCD without failures BRANCH=cr50 Change-Id: Ia8bb207a4407733f3cf77c52ac9063cc7bec3f94 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881752 Reviewed-by: Keith Short <keithshort@chromium.org>
* common: add ceil_for function to math_util.hLeifu Zhao2019-10-311-0/+11
| | | | | | | | | | | | | | | | | | During code review for tgl rvp enablement, found it is better to add ceil_for function to math_util.h. BUG=none BRANCH=none TEST=successfully compile for arcada Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: Iee350881c88e923c7a70317a9b8d75ee6104dba0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1873349 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* tcpm/fusb302: implement low power modeTing Shen2019-10-312-1/+11
| | | | | | | | | | | | | | | | | Implement tcpc_low_power_mode to reduce power consumption in G3. BUG=b:142760774 TEST=measure power consumption on jacuzzi. verify that power consumption is reduced by 3~4mW see b:142760774 comment 3 for more detail. BRANCH=master Change-Id: I04436d3baaa97b7c049ae3f3d9a9510e5a2024d9 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880773 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
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