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* endeavour: initial build from kalista/karmastabilize-12669.BJeff Chase2019-11-128-0/+1512
| | | | | | | | | | | | BUG=b:143780700 TEST=emerge-endeavour chromeos-ec Change-Id: Ib2cec6df3ab6a89a1b7bb278f231cb6b6da4f3ce Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893543 Tested-by: Jeff Chase <jnchase@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jeff Chase <jnchase@google.com> Auto-Submit: Jeff Chase <jnchase@google.com>
* flash_ec: enable UUT (UART) programming from microJett Rink2019-11-111-0/+27
| | | | | | | | | | | | | | | | | | | CL:1884410 adds the necessary dut control for servo micro that depends on the new servo micro console command (CL:1884190). If you make the appropriate rework on servo micro to control the DIR2 pin on the level shifter for the EC UART with TP1, then flash EC will successfully flash an EC using UUT (UART) with servo micro device. BRANCH=none BUG=b:143163043 TEST=flashed phaser using reworked servo_micro Cq-Depend:chromium:1884410 Change-Id: Ic45abb32d20f5c357d1fef154feea31cabb17672 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1884252 Reviewed-by: Keith Short <keithshort@chromium.org>
* rollback: Remove unused rollback_lock functionTom Hughes2019-11-111-26/+0
| | | | | | | | | | | | | | Use of the rollback_lock function was removed in https://crrev.com/c/479176. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I15bfeba9b169c7b0fae8d3c9423bc2f4817d52d8 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902460 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* stm32: Document flash layout for 1 MB Flash (STM32F412)Tom Hughes2019-11-111-1/+8
| | | | | | | | | | | | | | | | STM32F412xE has 512 KB flash STM32F412xG has 1 MB flash https://www.st.com/resource/en/datasheet/stm32f412cg.pdf BRANCH=none BUG=none TEST=make buildall -j Change-Id: I260659a1de62f3e79f427dd38ca831b4cabed448 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902463 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* helios: Fix battery discharge FET access config settingScott Collyer2019-11-111-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The batteries for helios specified register 0x44 as the register address that contains the status of the discahrge FET. That is correct for the TI fuel gauge. However, address 0x44 is in the manufacturer access region and therfore .mfgacc_support field needs to be set. However, register 0x0 mirrors the lower 16 bits of mfgacc reg 0x44, so an alternate solution is to change the reg_addr field to 0x0 and keep the regular smart battery register access method. In addition, this CL also removes dependency on the charge FET for battery disconnect state as that really only depends on the discharge FET being active so the battery can supply power to the system. BUG=b:136970148 BRANCH=None TEST=Put helios in ship mode via 'cutoff' on EC console. Then after waiting 30 seconds apply external AC power. Verfied that the discharge FET is initially disabled, then gets enabled as the battery wakes up. 2019-11-08 14:48:54 [3.428296 Batt disconnected: reg 0x6301 2019-11-08 14:48:54 [3.428843 found battery in disconnect state] 2019-11-08 14:48:54 [3.678447 Batt disconnected: reg 0x6301 2019-11-08 14:48:54 [3.678995 found battery in disconnect state] 2019-11-08 14:48:55 [4.427645 charge_manager_leave_safe_mode()] 2019-11-08 14:48:55 [4.434650 Battery 99% (Display 100.0 %) / ??h:?? to full] Prior to this fix this register was reading back 0x16 always. Change-Id: I8fbcdeb55f692796ced034c3c95db94fafdc908e Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906995 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* common: Refactor motion_sense_fifoYuval Peress2019-11-118-177/+691
| | | | | | | | | | | | | | | | | This change refactors the motion_sense_fifo to uniformly prefix all the functions to avoid collisions. It also adds several unit tests and fixes a few bugs with the fifo logic. BUG=b:137758297 BRANCH=kukui TEST=buildall TEST=run CTS on arcada, kohaku, and kukui TEST=boot kohaku (verify tablet mode works as expected) Change-Id: I6e8492ae5fa474d0aa870088ab56f76b220a73e3 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1835221 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* EC: Do not clear wake only events on resume from S3.Ravi Chandra Sadineni2019-11-111-6/+10
| | | | | | | | | | | | | | | | | | On path to S3, coreboot sets SCI and SMI mask to 0. It also sets appropriate wake mask. It then clears all pending events so as to prevent early wake (chromeec_smi_sleep). Thus the current resume hook to clear non SCI/SMI events would clear all events when resuming from S3 as SCI/SMI mask are set to zero. This change thus fixes the same. BUG=b:65976859 BRANCH=NONE TEST=Tested suspend/resume with wakeup count on grunt. Change-Id: Iea7652d1bdd122c2e66f52e2d8d0a6b7f2854c22 Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879517 Reviewed-by: Todd Broch <tbroch@chromium.org>
* baseboard/kukui: fix pogo extpower statusYilun Lin2019-11-113-5/+27
| | | | | | | | | | | | | | | | On krane, POGO provide extpower when only connects to a dock, so we should check if it's connecting to a dock, rather than checking POGO_VBUS_PRESENT only. TEST=see battery LED is off when connects to keyboard, and LED on when connets to a USB-C charger. BUG=b:144137508 BRANCH=kukui Change-Id: Iab38590780b1e86149287fb9985c8ffa625b016f Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1907670 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* power/mt8183: Need 1s pwrbtn press to exit off stateYilun Lin2019-11-114-6/+24
| | | | | | | | | | | | | | | | | | To prevent mispressed cases, we decide to increase the power button press boot time to at least 1s. TEST=aps; powerbtn $sec; where $sec is between 0~1000 and see it won't boot TEST=aps; powerbtn $sec; where $sec > 1000 and see it boot TEST=aps; ensures the physical power button press is working as expected. BUG=b:131856041 BRANCH=kukui Change-Id: Ie3099ba9639a729cee77b7d444a459fbef72733d Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906387 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Enable double tap host detection in kukuiHeng-Ruey Hsu2019-11-112-1/+27
| | | | | | | | | | | BUG=b:135575671 BRANCH=none TEST=AP can receive mkbp event when double tap is triggered Change-Id: I35abf2a62d4980c9b9232c28a72c5ba624142270 Signed-off-by: Heng-Ruey Hsu <henryhsu@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1772867 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Add double tap and make motion sense wake up apHeng-Ruey Hsu2019-11-113-6/+14
| | | | | | | | | | | | | | | Change to use CONFIG_GESTURE_DETECTION_MASK since CONFIG_GESTURE_SENSOR_BATTERY_TAP and CONFIG_GESTURE_SENSOR_DOUBLE_TAP both define it. BUG=b:135575671 BRANCH=none TEST=build pass. EC can receive double tap interrupt. Change-Id: I6eec40ef7405ec0653ff62dbce98f975cb19e332 Signed-off-by: Heng-Ruey Hsu <henryhsu@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1710210 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Fix skip interrupt logic for host eventHeng-Ruey Hsu2019-11-111-4/+10
| | | | | | | | | | | | | | | | | If CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK and CONFIG_MKBP_EVENT_WAKEUP_MASK are defined at the same time, |skip_interrupt| will be set for non host events. Add a check to handle it when |events_to_add| is MKBP host event. BUG=b:135575671 BRANCH=none TEST=CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK and CONFIG_MKBP_EVENT_WAKEUP_MASK work as expected. Change-Id: Iff72b0e276b63a211c249b3d1a92c0303012684e Signed-off-by: Heng-Ruey Hsu <henryhsu@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1903630 Reviewed-by: Jett Rink <jettrink@chromium.org>
* volteer: set battery I2C speed to 100 kHzKeith Short2019-11-111-1/+1
| | | | | | | | | | | | | | | | The battery fuel gauge only support I2C bus speeds up to 100 kHz. BUG=none BRANCH=none TEST=make buildall TEST=verify communication with battery on volteer Change-Id: Ie170d42844707a8d3b74876cf25e3b8a2eae17e8 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902692 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* puff: Update gpio list with unused pins.Andrew McRae2019-11-101-7/+35
| | | | | | | | | | | | | | | | Declare the unused GPIO pins so that they can be placed into the lowest power state. BRANCH=none BUG=b:143189339 TEST=EC buildall Change-Id: I9ec6f339456a08e2f333733e31d84e50cba8d6b3 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906388 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* volteer: add charger supportKeith Short2019-11-103-16/+8
| | | | | | | | | | | | | | | | Configure ISL9241 charger on Volteer. BUG=b:140557020 BRANCH=none TEST=make buildall Change-Id: I96f379cbb2adb7d46a79c9d177930e1ff4e0fa63 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1896649 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* chip/stm32: reinstate static and use EC idiom for alignmentPatrick Georgi2019-11-091-2/+2
| | | | | | | | | | | | | | | | | | | During my bug hunt I had to remove the static attribute. While that wasn't part of the fix, it slipped through. Also, Daisuke pointed out that the standard idiom in the EC codebase is __aligned instead of using the full __attribute__ statement, so switch over. BUG=none TEST=sweetberry gcc8 build still runs Change-Id: I106a8a2df3d6b56bfaba9819228ea7913029f707 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1905767 Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
* volteer: add initial battery supportKeith Short2019-11-098-6/+155
| | | | | | | | | | | | Add ODM specified 62 Wh battery. BUG=b:143477210 BRANCH=none TEST=make buildall Change-Id: I7c3292bbd23405781207366981c2af03b6d4624a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1896648
* board/garg: Configure the number of USB PD portsKarthikeyan Ramasubramanian2019-11-091-0/+8
| | | | | | | | | | | | | | | | | | | For HDMI SKU, there is one less USB PD Port compared to the other SKUs. Implement the board specific helper function to return the number of USB PD ports. This will ensure that the PD firmware update is not initiated on that port. BUG=b:140816510, b:143196487 BRANCH=Octopus TEST=make -j buildall; Boot to ChromeOS with and without a monitor plugged into HDMI port. Change-Id: I2f582372de35bb7669c0607b41a5ddc42abfc52c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879339 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/stm32/system: Fix the BUILD_ASSERT for CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-091-1/+1
| | | | | | | | | | | | | | | | | Some boards have CONFIG_USB_PD_PORT_MAX_COUNT defined as 3. Fix the concerned build assert. BUG=None BRANCH=None TEST=make -j buildall; Boot to ChromeOS in bobba(2A + 2C config) and garg(2A + 1C + 1HDMI config). Change-Id: I4dc949b69dbb3986acc5aa0444c6056268f815f7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898686 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Add a board specific helper to return USB PD port countKarthikeyan Ramasubramanian2019-11-0928-85/+179
| | | | | | | | | | | | | | | | | | | | | Certain SKUs of certain boards have less number of USB PD ports than configured in CONFIG_USB_PD_PORT_MAX_COUNT. Hence define an overrideable board specific helper to return the number of USB PD ports. This helps to avoid initiating a PD firmware update in SKUs where there are less number of USB PD ports. Also update charge manager to ensure that absent/ invalid PD ports are skipped during port initialization and management. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS in bobba(2A + 2C config) and garg(2A + 1C + 1HDMI config). Change-Id: Ie345cef470ad878ec443ddf4797e5d17cfe1f61e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879338 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* printf: be consistent using PRINTF_TIMESTAMP_NOWVadim Bendebury2019-11-091-2/+1
| | | | | | | | | | | | | | | | | PRINTF_TIMESTAMP_NOW is used to indicate that %pT format specifier means 'current time'. Let's use it at the point where format is analyzed to be consistent with the rest of the EC tree. BRANCH=none BUG=none TEST=make buildall succeeds, 'ccprintf ("%pT", PRINTF_TIMESTAMP_NOW);' still prints the current time. Change-Id: I42e80039a4335015f5504830070ca36abfb2487c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906994 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org>
* ish: board enablement for tgl rvp platformLeifu Zhao2019-11-095-0/+223
| | | | | | | | | | | | | | | | | Board level enablement for tgl rvp platform. BUG=b:141519691 BRANCH=none TEST=tested on tgl rvp Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I5a2ce355ca7c384c82500d0295035fae3cdb183e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846787 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* ish: chip enablement of ish5.4 on tgl rvp platformLeifu Zhao2019-11-0914-45/+344
| | | | | | | | | | | | | | | | | Chip level enablement of ish5.4 on tgl rvp platform. BUG=b:141519691 BRANCH=none TEST=tested on tgl rvp Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I3f6249e1816d81deec0420a12b093918ee7fbddc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846788 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* hatch_fp: Move SLP_S0_L for Hatch Rev 2.8Craig Hesling2019-11-081-2/+2
| | | | | | | | | | | | | | | | | | | | | Previous schematic was Hatch Rev 2.6 (commit e36c8b3683475b853c21564ddabc3ec90ee64f75 in hatch ee-git): http://go/hatch-schematic-rev-2.6 New schematic is Hatch Rev 2.8 (commit defe790e8d1c863de2ec04ee50f285e270038848 in hatch ee-git): http://go/hatch-schematic-rev-2.8 BRANCH=none BUG=b:144004439 TEST=make buildall -j Change-Id: Ia40c4149f9c9d68c39e8235fec9a949347ed9c27 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1904652 Tested-by: Craig Hesling <hesling@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Craig Hesling <hesling@chromium.org>
* stm32f4: Enable gpio port clocks that are usedCraig Hesling2019-11-084-7/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can reduce the power draw of the MCU by limiting which GPIO port clocks are enabled. This CL uses the gpio.inc to determine the minimal set of GPIO ports that need to be enabled/clocked. Only these ports have their clocks enabled at boot. Other stm32 chip variants in EC simply enabled all GPIO port clocks at boot init. Thank you to Ravi Chandra Sadineni for identifying this optimization and validating. For more context, see crrev.com/c/1888116, which this CL replaces. BRANCH=nocturne,hatch BUG=b:130561737 TEST=make buildall -j TEST=make BOARD=bloonchipper # Connect dragonclaw dev board over servo micro sudo servod --board=bloonchipper --config bloonchipper_rev0.1.xml & ./util/flash_ec --board=bloonchipper minicom -D $(dut-control raw_fpmcu_uart_pty | cut -d: -f2) > sysinfo # Check that we are in RW Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: Iad51b11eb5959b5d502320560b9ebda7e614d97e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1890924 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* hatch_fp: Switch to UNUSED pins mechanismCraig Hesling2019-11-081-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL enables UNUSED pins for hatch_fp. This places the unused/unconnected pins in the lowest power state. Using the UNUSED pins mechanism should be functionally equivalent to the previous method of declaring these pins as analog inputs. See crrev.com/c/1894242 for implementation details. BRANCH=nocturne,hatch BUG=b:130561737 TEST=make buildall -j TEST=make BOARD=bloonchipper # Connect dragonclaw dev board over servo micro sudo servod --board=bloonchipper --config bloonchipper_rev0.1.xml & ./util/flash_ec --board=bloonchipper minicom -D $(dut-control raw_fpmcu_uart_pty | cut -d: -f2) > sysinfo # Check that we are in RW Change-Id: I412118287893ec63cef42c6c190d0a4755de06cb Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1900122 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* stm32f4: Implement UNUSED pinsCraig Hesling2019-11-081-0/+14
| | | | | | | | | | | | | | | | | | | | | | This CL adds support for UNUSED pins to the STM32F4 family of chips. This places the unused/unconnected pins in the lowest power state. In this case, ST recommends that you configure the pin as analog-in to disable the schmitt trigger logic. This codified the work done in crrev.com/c/1883127 . The CL should have no functional change for boards that have not specified UNUSED pins in their gpio.inc. BRANCH=nocturne,hatch BUG=b:130561737 TEST=make buildall -j Change-Id: I444b868b277b016a896e410dccae84429b68839e Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894242 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* gpio: Add UNUSED declaration for gpio.incCraig Hesling2019-11-083-0/+48
| | | | | | | | | | | | | | | | | | | | This new gpio.inc macro is intended to mark pins that are unused on a given board. This allows the chip implementation to configure them for the lowest power configuration. This CL brings immediate functional change. A reference implementation is provided for the STM32F4 chip family in crrev.com/c/1894242. BRANCH=nocturne,hatch BUG=b:130561737 TEST=make buildall -j Change-Id: I0bc0a63401ae8f3bba4108b5b9f9ced26785f2bc Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898796 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* puff: Finalise EC LED configuration for puff.Andrew McRae2019-11-082-4/+17
| | | | | | | | | | | | | | | | Configure the PWM channels for the red and green LED. LED handling has been copied from fizz. BRANCH=none BUG=b:144063385 TEST=EC buildall, tests Signed-off-by: Andrew McRae <amcrae@google.com> Change-Id: I6883135387f0a6e49661e93cc5358a8e6c8c7f68 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902893 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* pd: Clarify flag commentsDenis Brockus2019-11-084-78/+142
| | | | | | | | | | | BRANCH=none BUG=b:141563840 TEST=make -j buildall Change-Id: Iaff605f5d93ccce26aec4d9e33be78017c7b9231 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906194 Reviewed-by: Jett Rink <jettrink@chromium.org>
* pd: Clear PE_FLAGS_PS_TRANSITION_TIMEOUTDenis Brockus2019-11-081-1/+1
| | | | | | | | | | | | | | | | The flag was being checked for being set and then if it was set it was being set again. The pattern everywhere in this situation is to clear the flag and not set it again. Looks like a typo that was not caught BUG=none BRANCH=none TEST=make buildall -j Change-Id: I18f52343e0583cd0eecc509b01337ab60804130d Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906193 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ec_commands: Force enum to be at least 16 bitsTom Hughes2019-11-081-3/+5
| | | | | | | | | | | | | | | | | | If the values in the enum can fit in a byte, the compiler can optimize the size of the enum to a byte. However, our protocol requires 16 bits, so define a max enum value that forces at least 16 bits. BRANCH=none BUG=b:144056522 TEST=make buildall -j Change-Id: I119d990f2775d8b970ec0ec15df1e451fc5dc45d Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902679 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* tglrvp: Add back the ALL_SYS_PWRGD signalVijay Hiremath2019-11-082-3/+3
| | | | | | | | | | | | | | Adding back the ALL_SYS_PWRGD signal which was removed as part of the CL:1881753. BUG=b:143373337 BRANCH=none TEST=powerinfo shows all signals Change-Id: I8ddfb0ed61963839cd657840b9a5b80cebb5da86 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1900125 Reviewed-by: Keith Short <keithshort@chromium.org>
* Kodama: SMP battery cannot be charged in over discharge statexiong.huang2019-11-083-3/+38
| | | | | | | | | | | | | | | | | | | | SMP battery uses HW pre-charge circuit and pre-charge current is limited to ~50mA. Once the charge current is lower than IEOC level within CHG_TEDG_EOC, and TE is enabled, the charging power path will be turned off. Charger vendor advice that disable EOC and TE when battery stays over discharge state, otherwise enable EOC and TE. BUG=b:142630134 TEST=Verified on both SMP battery and Celxpert battery in over discharge state, all passed. BRANCH=kukui Change-Id: I7d6907d54ab555587a489333350de6e9aeffe60e Signed-off-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893901 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* volteer: Configure ADC channelsKeith Short2019-11-083-4/+43
| | | | | | | | | | | | | | | | | | Configure ADC channels for temperature sensors. enum adc_channels is required by the isl9241 charger support. Addtional changes are still needed to support EC thermal capabilties. BUG=b:143768086 BRANCH=none TEST=make buildall Change-Id: Ia34464e56185e1693dd4c8aed378d7703c290742 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1896640 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* pd: Remove EMarker Cable ProbeSam Hurst2019-11-082-167/+17
| | | | | | | | | | | | | | | The current PD3.0 EMarker cable probe functionality is unstable. Remove and add back as a feature after the PD3.0 code base is stable. BRANCH=none BUG=b:144093713 TEST=make -j buildall Used total phase to verify that the cable was not probed. Change-Id: I2906a16c96faff9d8107ef19286acdbe60869180 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1904157 Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: fix vbus discharge path for GPIOJett Rink2019-11-075-15/+49
| | | | | | | | | | | | | Code on Tot assumes that port count was the port to discharge instead of port parameter BRANCH=none BUG=none TEST=verified with unit test (in this CL) Change-Id: I17658a0c555f9cea56fa4ec1652e0faf62e3d6cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1896125
* servo_micro: add usart cmd to hold pins lowJett Rink2019-11-073-4/+105
| | | | | | | | | | | | | | | | | | | | | To enabled UART (UUT) programming mode for some ECs, we need to drive the EC_TX_SERVO_RX line low while the EC is rebooting. Add a console command that is controllable by dut-control that will drive the UART pins low while the UART is disabled, until the command to re-enable the UART is sent on the console. Also, remove unnecessary alternate mode initialization for USART4 (UART3). BRANCH=firmware-servo-11011.B BUG=b:143163043 TEST=flashed phaser with reworked servo_micro Change-Id: I1af1af7b48bf446936211740e16008a80ab2a39f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1884190 Reviewed-by: Keith Short <keithshort@chromium.org>
* Drop LTO workaround from sweetberryStefan Reinauer2019-11-071-5/+0
| | | | | | | | | | | | | | | | Because it breaks external builds such as coverity builds. The issue needs to be fixed differently. BUG=b:132204142 TEST=flash on sweetberry and see usb endpoints work BRANCH=none Change-Id: I2ee1789e12dd5240fac4bf97a2638efa85446df6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1851105 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Auto-Submit: Stefan Reinauer <reinauer@chromium.org>
* g: board_id: allow setting bid type if only flags are setMary Ruthven2019-11-071-13/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's ok to set the board id type if it's blank. It doesn't matter if the flags are set. Use the given flags if the flags are empty or use the existing flags if they're already set. BUG=b:143649068 BRANCH=cr50 TEST=manual eraseflashinfo gsctool -i ZZAF:0x7f7f - SUCCEEDS. Board ID: 5a5a4146:a5a5beb9, flags 00007f7f gsctool -i ZZAF:0x7f7f - FAILS Board ID: 5a5a4146:a5a5beb9, flags 00007f7f eraseflashinfo gsctool -i 0xffffffff:0x3f80 - SUCCEEDS. Board ID: ffffffff:ffffffff, flags 00003f80 gsctool -i ZZAF:0x7f7f - SUCCEEDS. Board ID: 5a5a4146:a5a5beb9, flags 00003f80 eraseflashinfo bid 0xffffffff 0x3f80 Board ID: ffffffff:00000000, flags 00003f80 gsctool -i ZZST:0x3f80 - FAILS. Board ID: ffffffff:00000000, flags 00003f80 update to image with BID TEST:ffff:10 eraseflashinfo gsctool -i 0xffffffff:0x3f80 - FAILS Board ID: ffffffff:ffffffff, flags ffffffff gsctool -i ZZAF:0x7f7f - FAILS Board ID: ffffffff:ffffffff, flags ffffffff gsctool -i ZZST:0x7f7f - SUCCEEDS. Board ID: 5a5a5354:a5a5acab, flags 00007f7f update to image with BID TEST:0:100 eraseflashinfo gsctool -i whitelabel - SUCCEEDS. Board ID: ffffffff:ffffffff, flags 00003f80 gsctool -i ZZST:0 - SUCCEEDS. Board ID: 5a5a5354:a5a5acab, flags 00003f80 Change-Id: I07de4721cb9cc9ad6e74a51e1794a49cb70f70fb Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892122 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* g: bid: show type is empty instead of an errorMary Ruthven2019-11-071-1/+1
| | | | | | | | | | | | | | | It's ok if type and type_inv are both empty. Only show an error if the board ID type isn't empty and the inversion is incorrect. BUG=none BRANCH=cr50 TEST=set whitelabel rlz and run 'bid' command. Make sure the warning isn't shown. Change-Id: I12b1e4b34559bc8b6ad482d9694c9dd143bfcd1c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892121 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* sn_bits: allow setting serial number if BID type is blankMary Ruthven2019-11-073-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:143649068 BRANCH=cr50 TEST=manual eraseflashinfo Board ID: ffffffff:ffffffff, flags ffffffff gsctool -S AAAAAAAAAAAAAAAAAAAAAAA1 succeeds eraseflashinfo gsctool -i 0xffffffff:0x3f80 Board ID: ffffffff:ffffffff, flags 0x3f80 gsctool -S AAAAAAAAAAAAAAAAAAAAAAA1 succeeds eraseflashinfo gsctool -i ZZAF:0x7f7f Board ID: 5a5a4146:a5a5beb9, flags 0x3f80 gsctool -S AAAAAAAAAAAAAAAAAAAAAAA1 fails Change-Id: I5d2a3f35c5c7e4e79cadbb3a6737e5db00f8ca5a Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892120 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* board_id: change the vc to allow setting only flagsMary Ruthven2019-11-071-1/+4
| | | | | | | | | | | | | | | If the board id type is 0xffffffff, hold off on erasing any type_inv bits until we get a type that isn't empty. BUG=b:143649068 BRANCH=cr50 TEST=Use gsctool -i 0xffffffff:0x3f80 to set flags to 0x3f80. Get the board id and make sure the rlz and rlz_inv fields are still 0xffffffff. Change-Id: I8243cb59f2560dc232bb982e1615271136d60f24 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892118 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* board_id: ignore erased bid type when checking headersMary Ruthven2019-11-072-12/+28
| | | | | | | | | | | | | | | | | We will be able to set the board id flags without setting the type. If only flags are set, then check the flags. If the type is set, also check the type. BUG=b:143649068 BRANCH=cr50 TEST=set flags to 0x3f80. Try to update to a ZZAF:0:0:0 image. Make sure it isn't rejected with board id type mismatch. Try to update to a prepvt image. Make sure it's rejected. Change-Id: Ie0efdd7b1b6d76f385688f75c0765c08cab3755c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892117 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* board_id: clean up/enhancementsMary Ruthven2019-11-071-5/+6
| | | | | | | | | | | | | | | | | Add type_inv to the bid command output. In the bid output you can't tell the difference between a board with type 0xffffffff and a empty type. Change the command output to show type and type_inv, so we can tell the difference. Remove unused clear_flag parameter BUG=b:143649068 BRANCH=cr50 TEST=run 'bid' Change-Id: I13b6ba472010fdf85f94cb4015a9bbc48531973d Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892115 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* sn_bits: use board_id_is_blankMary Ruthven2019-11-071-1/+1
| | | | | | | | | | | | | | Use the standard board_id_is_blank function to check if the board id is blank. BUG=b:143649068 BRANCH=cr50 TEST=set the serialnumber Change-Id: If4e50a548ec2a4747b7bc291f93f170e28eea949 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892114 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* Trembyle: Add more IOEX GPIO definitionsEdward Hill2019-11-071-2/+10
| | | | | | | | | | | | BUG=none BRANCH=none TEST=build Change-Id: I64c5b46367774163f532bbcb9097657e2b83ad9f Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1904153 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* pd: Comment all flagsSam Hurst2019-11-074-75/+104
| | | | | | | | | | | | | | | | All of the flags in all layer needs comments of what the flags means and a potential usage. all TC_FLAGS_*, PR_FLAGS_* and PRL_FLAGS_* BRANCH=none BUG=b:141563840 TEST=make -j buildall Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I520daa841a61e36a8a6b394e0f96b198b16ad561 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1904148 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org>
* dratini/dragonair: add new SKUDevin Lu2019-11-071-3/+7
| | | | | | | | | | | | | | add unprovisioned SKUID to support kblight and convertible for pre-flash cbi. add SKU ID: 23 (Convertible, TS, Stylus) BUG=b:142987639, b:143994766 BRANCH=none TEST=make buildall -j. Change-Id: Ie8d4b611d8073ff993a94699d832ada6830a2771 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902892 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* baseboard/kukui: Increase UART TX buffer size to 8192Yilun Lin2019-11-071-1/+1
| | | | | | | | | | | | | | | To keep buffer overflow logs. TEST=make buildall BUG=none BRANCH=kukui Change-Id: I2db611f9296aa03cfb97932f3c816003a2610ecb Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1899654 Tested-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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