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* Cr50: SAFE MODE: all GPIOs are inputs for Kevin0stabilize-7978.Bstabilize-7978.18.BBill Richardson2016-02-271-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | Except for the console UART TX and the SPI slave MISO, this CL configures all the formerly output GPIOs as inputs. The Cr50 firmware at this point doesn't actually DO anything useful with the GPIOs that would normally be outputs on the Kevin board (we don't assert SYS_RESET, or EC_FLASH_SELECT, for example), and the board *should* be designed so that no important signals like those just float. By using this configuration, we're trying to limit the potential harm done by unexpected schematic changes. Once the system boots, we should be able to use the SPI bus to update Cr50 to add more features, such as testing Cr50 GPIOs individually. BUG=chrome-os-partner:49952 BRANCH=none TEST=make buildall, run on Cr50 board Change-Id: I1f0a164e2cd3e4f632b862e33dba69f0dc944322 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329557 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: use the correct signer invocation optionsVadim Bendebury2016-02-272-1/+2
| | | | | | | | | | | | | | | The new signer command line option should be used by some boards, not all of them. Add it for cr50 for now. BRANCH=none BUG=none TEST=verified that --cros is added to the command line when cr50 blobs are signed, and that the signed blob boots fine on b1. Change-Id: Ibc38cc6233b57838129ae7d554921c1bae0e6b8c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329595 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: signer: sync up with upstreamVadim Bendebury2016-02-274-302/+264
| | | | | | | | | | | | | | | This change just copies files shared between two repositories which have changed since the last sync up. This time it is as of @CL85098. BRANCH=none BUG=none TEST=the signed image boots fine on the b1 board. Change-Id: I7a1d1b344119e6f6729a38bbea04da75f2d3371c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329407 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Debug: Add pinmux and gpiocfg commandsBill Richardson2016-02-271-0/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds two debugging commands to decode the PINMUX and GPIO routings without having to look at a bunch of hex values. They can easily be removed to save space, but they're kind of handy for now. BUG=chrome-os-partner:49952 BRANCH=none TEST=make buildall, and test on Cr50 Run the "pinmux" and "gpiocfg" commands. Verify that the output reflects the desired configs found in gpio.inc I get this: > pinmux 40060000: DIOM0 5 IN GPIO0_GPIO4 40060008: DIOM1 6 IN GPIO0_GPIO5 40060010: DIOM2 0 IN PU 40060028: DIOA0 70 UART0_TX 40060030: DIOA1 0 IN 40060038: DIOA2 0 IN 40060040: DIOA3 2 IN GPIO0_GPIO1 40060050: DIOA5 0 IN 40060058: DIOA6 0 IN 40060060: DIOA7 3 IN GPIO0_GPIO2 40060088: DIOA12 0 IN 400600a0: DIOB0 33 IN 400600a8: DIOB1 34 IN 400600b0: DIOB2 0 IN 400600b8: DIOB3 74 UART1_TX 400600c0: DIOB4 0 IN PD 400600c8: DIOB5 78 UART2_TX 400600d0: DIOB6 0 IN 400600d8: DIOB7 1 IN GPIO0_GPIO0 400600f8: GPIO0_GPIO0 3 DIOB7 400600fc: GPIO0_GPIO1 22 DIOA3 40060100: GPIO0_GPIO2 18 DIOA7 40060104: GPIO0_GPIO3 20 DIOA5 40060108: GPIO0_GPIO4 30 DIOM0 4006010c: GPIO0_GPIO5 29 DIOM1 40060110: GPIO0_GPIO6 28 DIOM2 40060208: UART0_RX 24 DIOA1 40060218: UART1_RX 8 DIOB2 40060228: UART2_RX 4 DIOB6 > gpiocfg GPIO0_GPIO0: read 0 drive 1 GPIO0_GPIO1: read 0 drive 0 GPIO0_GPIO2: read 0 drive 0 GPIO0_GPIO4: read 0 drive 0 GPIO0_GPIO5: read 0 drive 0 > Note that we skip GPIO0_GPIO3 and GPIO0_GPIO6 because they're neither outputs nor interrupts. All the GPIOs can do that. Change-Id: I93b881bfd93dc100096bbd005a6c31b2669eda2f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329527 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Configure GPIOs for Kevin proto0Bill Richardson2016-02-273-4/+77
| | | | | | | | | | | | | | | BUG=chrome-os-partner:49952 BRANCH=none TEST=make buildall, run on Cr50 board It's kind of hard to test GPIOs that aren't attached to anything, but I've examined all the PINMUX controls and ARM GPIO settings, and I *think* they're right. Change-Id: I66ae94118f73c41193c6ca5c0af9708f6cc8a3e8 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329526 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: cleanup: Remove some unneccessary codeBill Richardson2016-02-272-11/+0
| | | | | | | | | | | | | | | Removing a declaration for a function that no longer exists, and deleting some extra PINMUX config that is also (and correctly) being done in the module that uses it (chip/g/sps.c). BUG=none BRANCH=none TEST=make buildall and test image on Cr50 Change-Id: Ie381862cfcd3c043ebf78171d18a51593b3677f7 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329525 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* lucid: add support to detect BC1.2 suppliersMary Ruthven2016-02-267-24/+138
| | | | | | | | | | | | | | | | Use built-in USB periperal to detect BC1.2 suppliers and update the charge manager. BUG=chrome-os-partner:48658 BRANCH=None TEST=manual for lucid. Use a samus as the supplier, and insert the charger into Lucid. Verify that it identifies it as SDP. Use a wall charger and verify that Lucid identifies it as DCP. Change-Id: I7842e9f75874f727837df5bfc28690662caf821c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329236 Reviewed-by: Shawn N <shawnn@chromium.org>
* oak: Enable TI OPT3001 ambient light sensor for rev5Ben Lok2016-02-263-0/+26
| | | | | | | | | | | | Refer to commit 3f2dc44158630f0ce93633c21df8daaddb2b7324, enable light sensor driver for oak rev5 BUG=chrome-os-partner:50312 Change-Id: I896cf99fd781f5d4d8dad206d43f5a3d8faeb9a2 Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/319271 Reviewed-by: Rong Chang <rongchang@chromium.org>
* glados_pd: Add WP_L input GPIO for future boardsShawn Nematbakhsh2016-02-253-1/+22
| | | | | | | | | | | | | | | | | | | | Future glados-derived boards are adding a WP_L GPIO input. Add support for this input, which will apply only if CONFIG_SYSTEM_UNLOCKED is not defined. Undefining CONFIG_SYSTEM_UNLOCKED will result in unpredictable WP GPIO behavior for all boards that currently exist, so it should only be undef'd right before MP FW is released. BUG=chrome-os-partner:50518, chrome-os-partner:50519 BRANCH=glados TEST=Verify 'ectool gpioget A13 --dev=1' always indicates a GPIO state '1' on an old chell_pd without WP_L input. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id50a13cce54bc2013d83613ce5599ffde6a6837b Reviewed-on: https://chromium-review.googlesource.com/329370 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* cleanup: Add warning comment to gpio.inc filesBill Richardson2016-02-2540-19/+122
| | | | | | | | | | | | | | | | | | | | | | | With commit e9883124ff16, a GPIO_INT macro was added. That change also required that all instances of GPIO_INT in a board's gpio.inc file come before any GPIO macros, or the interrupt handler wouldn't work properly. This CL just adds a warning comment about requirement to all gpio.inc files. BUG=chromium:471331 BRANCH=none TEST=make buildall, test image on Cr50 This is a change to comments only. There is no new behavior to verify, although I did run try out one new image just to be sure nothing stupid happened. Change-Id: I83f7819929a53bce3a8bae04d15b3ee3bda11738 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329334 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Remove GPIOs left over from FPGA boardsBill Richardson2016-02-252-80/+4
| | | | | | | | | | | | | | | | | | Let's just get rid of the old GPIOs before configuring the new ones. BUG=chrome-os-partner:49952 BRANCH=none TEST=make buildall, test on Cr50 B1 boards None of the FPGA buttons or LEDs are present on the B1 board, so there's no visisble difference between talking to non-existent components and NOT talking to non-existent components. Change-Id: I839982ac06a983879f0240635442b51f794daffb Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329267 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Cleanup some of the GPIO handling codeBill Richardson2016-02-254-19/+16
| | | | | | | | | | | | | | | | | Just a bit of refactoring. This cleans up some macro definitions and error checking, and removes a duplicate list of GPIO signal names. BUG=none BRANCH=none TEST=make buildall, test on Cr50 No functional changes, so nothing new to test. Change-Id: Iecacc5a0b7da02aa9d0b94f171c70f0b73e8edd5 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329303 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* mec1322: port80: Disable port80 interrupt and timer after timeoutShawn Nematbakhsh2016-02-251-29/+47
| | | | | | | | | | | | | | | | | | | | port80 activity usually comes in bursts during AP boot and then goes quiet. For power savings, turn off the port80 interrupt and timer after no activity is seen for 30 seconds. BUG=chrome-os-partner:50175 TEST=Boot chell, verify port80 prints are seen. Verify timer + interrupts are disabled ~30 seconds later. Power down, power up, and verify port80 prints are seen once again. BRANCH=glados Change-Id: Iea091d73aa0c6e9cfb36240d68e31a20425cea45 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327256 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* it8380dev: util: Fix iteflash flash issueDonald Huang2016-02-251-1/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix iteflash flash issue. 1. Avoid EC watchdog reset while flashing. 2. Do watchdog reset after flashing. BRANCH=none BUG=none TEST=Test OK on ITE8390CX. You can run "make -j BOARD=it8380dev" to build ec.bin and flash the ec.bin via "sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin" /* ==SNAPSHOT START== */ (cr) ((29b0840...)) donald@donald-nb ~/trunk/src/platform/ec $ sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin Waiting for the EC power-on sequence ...CHIPID 8390, CHIPVER 82, Flash size 256 kB Done. CHIPID 8390, CHIPVER 82, Flash size 256 kB Erasing chip... /100% Writing 262144 bytes at 0x00000000 Done. Verify 262144 bytes at 0x00000000 -100% Verify Done. /* ==SNAPSHOT END== */ Change-Id: I43fc5124f3854a516df17fab78649d4b083ed9b0 Signed-off-by: Donald Huang <donald.huang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/328873 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Fix USB two-stage control transfersBill Richardson2016-02-251-5/+6
| | | | | | | | | | | | | | | | | | | | This cleans up a great deal of flakiness that we've seen on the USB for a long time. I was misinterpreting and/or misimplementing some of the documentation. This seems to make all the difference. BUG=chrome-os-partner:50370 BRANCH=none CQ-DEPEND=CL:328979,CL:*249229 TEST=make buildall, and test on Cr50 Before this CL, the USB connection would only work on USB2.0 buses, connected directly to my workstation. With this CL, it works on USB2.0, USB3.0, through hubs, etc. Yay! Change-Id: Icfa1910bf34f73332e2f8fc4f0d6789541549493 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329262 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* g: Clean up pinmux initializationAnton Staaf2016-02-252-99/+93
| | | | | | | | | | | | | | | | | | | | | | Now that the pinmux information isn't packed into the GPIO alternate function table, we can expand it a bit and give the fields nice names, making the code easier to read and removing a number of bit packing macros defined in registers.h. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Verified on cr50 hardware CQ-DEPEND=CL:*249229 Change-Id: I9984bc37faf69b1ba9f1ba66a49596dd22e3b601 Reviewed-on: https://chromium-review.googlesource.com/328979 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* util: ec3po: Implement auto interrogation mode.Aseda Aboagye2016-02-242-10/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commits adds support for the auto interrogation mode. The auto mode continually scans across the console output looking for a string that is printed upon reboot. The string is: Console is enabled; type HELP for help When the EC-3PO interactive console sees this string, it knows that the current EC image is not enhanced and therefore no longer needs to perform an interrogation after every command. Additionally, the enhanced EC images will print a slightly different string than from above so that the console can detect enhanced EC images as well. By default, the console interpreter will now start up in the 'auto' mode instead of the 'always' mode that it used to. This removes the 300ms delay after each console command. BUG=chromium:588611 BRANCH=None TEST=./util/ec3po/run_tests.sh TEST=cros lint --debug util/ec3po/console.py TEST=cros lint --debug util/ec3po/console_unittest.py Change-Id: Iec7ebd437ee363c2fc01b8b1adade485a0bff7a9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/329054 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* jerry: Increase UART TX buffer size.Aseda Aboagye2016-02-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Found out that the string that is printed from console_init() doesn't show up on the EC console for jerry. It seems that perhaps due to the priority of the console task and the numerous prints during boot, that print never makes it to the TX buffer. Currently, there's about 7200 bytes available in the shared memory region, which indicates that there's still a lot of free space. Therefore, increase the UART TX buffer size. BUG=None BRANCH=None TEST=Flash jerry and verify that 'console is enabled' string shows up on the EC console. TEST=make -j buildall tests Change-Id: Id0603a3b758b5c600d0b59f27040ead2ce48bbaf Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/329180 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: console: Change console_init() string.Aseda Aboagye2016-02-231-0/+4
| | | | | | | | | | | | | | | | | | | | | For enhanced EC images, change the string telling the user that the console is enabled. This is such that EC-3PO can distinguish between non-enhanced ECs and enhanced ECs during EC boot. BUG=chromium:588611 BRANCH=None TEST=Build for chell with CONFIG_EXPERIMENTAL_CONSOLE and verify that the new string is printed. TEST=Repeat above test but without the config option and verify that the old string is printed. TEST=make -j buildall tests Change-Id: Ic8ed0a028ecb701b999fa6c6a376704f375dbc62 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/329161 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: Don't source VBUS when forcing sink rolestabilize-7956.BShawn Nematbakhsh2016-02-231-0/+2
| | | | | | | | | | | | | | | | | | | | | When forcing a sink role (eg. on transition from S3->S5), make sure we're not sourcing VBUS. Otherwise, if a power source is attached, we will fail to charge from it, due to the inability to sink and source VBUS simultaneously. BUG=chrome-os-partner:49544 chrome-os-partner:50343 TEST=Boot chell, attach USB-C peripheral, then power down chell. Remove USB-C peripheral, attach zinger, and verify PD negotiation + charging succeeds. BRANCH=glados Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I5fb9b0eb26e61daa93a167d6a3e9aaf4e4eeed39 Reviewed-on: https://chromium-review.googlesource.com/327727 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: upgrade: fix debug messages to show address instead of offsetVadim Bendebury2016-02-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | Debug messages generated by the firmware upgrade extension command show flash offsets (the values used when calling flash API), but the user is more interested in absolute addresses, as they are reported by some other debug printouts. Change fw_upgrade_command_handler() debug output to report absolute flash addresses. BRANCH=none BUG=chrome-os-partner:37754 TEST=ran upgrade test, observed proper addresses reported: fw_upgrade_command_handler: programming at address 0x84000 fw_upgrade_command_handler: programming at address 0x84400 ... Change-Id: I8a6cd6020e5ddcbf41f5931cf7632fc598d4745e Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/328810 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: add in-place decrypt support for AES-CFBnagendra modadugu2016-02-231-36/+17
| | | | | | | | | | | | | | | | | | | | | The api _cpri__AESDecryptCFB is expected to support in-place decryption, which the previous implementation did not support (i.e. part of the input was was written to prior to being read). Switch to CTR mode to ECB mode in order to support in-place decrypt. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=corresponding TPM2 test suite command passes Change-Id: I8a096bdab7a1ca130a07d992c9fce3fc19016e17 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/328761 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* Lars_PD: GPIO correctionKyoung Kim2016-02-221-1/+1
| | | | | | | | | | | | | | | | Reconfigure EC_INT pin due to external PU for lower suspend power BRANCH=firmware-glados-7820.B BUG=chrome-os-partner:50159 TEST=measure PD power at S3/S0ix/SOC-G3 Change-Id: I94c89113e4feb12b63fbe402a6c6cfe0c2d10394 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/327995 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: test: do not leave the bootsrtap pin in the wrong stateVadim Bendebury2016-02-221-3/+1
| | | | | | | | | | | | | | | | | | | | | | | It was observed that the b1 test board falls into bootstrap mode once the reset button is pressed after a firmware upgrade. The reason turns out to be that the wrong lead was considered to be the reset pin, the BIO4, responsible for bootstrapping, was used instead of the reset pin. Come to think of it, there is no need to reset the device each time the FTDI SPI interface is initialized. Let's just drive the bootsrtap pin to the correct level and not generate the reset pulse at all. BRANCH=none BUG=chrome-os-partner:37754 TEST=pressing the reset button on the b1 board now properly restarts the device. Change-Id: I123dad8043807c8ff01e12254f9efc2f0d1aaa13 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/328811 Reviewed-by: Marius Schilder <mschilder@chromium.org>
* GPIO: Remove gpio_alt_funcs table from common headerAnton Staaf2016-02-223-35/+32
| | | | | | | | | | | | | | | | | | | | Now that the cr50 no longer uses this array to store its pinmux config we can move it out of the header file, removing it from the public interface for GPIO code. This allows us to start modifying this struct more easily. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I9b4ca8b678b102bb9b63ccffe23bf2dc87aeb44a Reviewed-on: https://chromium-review.googlesource.com/328824 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: Switch from ALTERNATE to PINMUX macrosAnton Staaf2016-02-222-26/+42
| | | | | | | | | | | | | | | | | | Previously the g chip and cr50 board abused the ALTERNATE macro to encode the pinmux configuration. This switches them over to using a PINMUX macro that is designed for this purpose. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I5c1f70b7aa92d87cc105e672aa66aee7f267c9a2 Reviewed-on: https://chromium-review.googlesource.com/328823 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* GPIO: Move definitions of GPIO_KB_INPUT and OUTPUTAnton Staaf2016-02-2221-39/+32
| | | | | | | | | | | | | | | | | | | | Previously these were often done in board.c files, which made it impossible to include the gpio.inc anywhere else. As part of refactoring the GPIO code we now need to be able to include gpio.inc from common/gpio.c. Moving these defines into gpio.inc makes them available wherever gpio.inc is included. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I28e7b5a1d40b113ae824b18f020b2d1e51e0c08a Reviewed-on: https://chromium-review.googlesource.com/328822 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* skylake: do not clear masks in S0ix -> S0 transitionArchana Patni2016-02-222-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | EC clears the SCI/SMI/Wake masks in the resume sequence for S3 and S0ix. This works in the S3 case because Coreboot reprograms the masks after EC. But in S0ix, these masks stay cleared forever. This means that no further events are sent to the host. This patch conditionally clears the masks only in the S3 transition. BRANCH=glados BUG=chrome-os-partner:48834 TEST=hostevent in EC console before and after S0ix to ensure SCI masks are preserved Change-Id: I23751680788ee7a239e321309a1334d37adc4f43 Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://chromium-review.googlesource.com/320191 Commit-Ready: Jenny Tc <jenny.tc@intel.com> Tested-by: Jenny Tc <jenny.tc@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Kunimitsu: Enable config REPLACE_LOADER_WITH_BSS_SLOWShobhit Srivastava2016-02-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | If during EC boot we have space issue in shared memory then ec hash calculation aborts and we cannot boot to RW. This patch enables the config option to reclaim space from little firmware loader. This leads to more shared memory availability and resolves the boot issue. BUG=chrome-os-partner:50127 BRANCH=glados TEST=Build/Flash and verify DUT boots to RW. Increase PD logging size to 512 and verify again that DUT boots to RW Change-Id: Ic49e37fbc83e12a52cadd9796c5ef6f47d8cf33f Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://chromium-review.googlesource.com/327656 Reviewed-by: Srinivas Kowtal <srinivas.kowtal@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 22f8c71aca4d5bf225e420507e34032eef2ea5c0) Reviewed-on: https://chromium-review.googlesource.com/328330 Commit-Ready: Divagar Mohandass <divagar.mohandass@intel.com> Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-by: Jenny Tc <jenny.tc@intel.com>
* Cr50: Slightly better USB error messagesBill Richardson2016-02-181-12/+12
| | | | | | | | | | | | | | | | | Change the report_error() macro that we use to indicate unhandled conditions so that it can take an integer argument. Sometimes that's useful. BUG=none BRANCH=none TEST=make buildall, try some USB stuff, everything still works No functional difference, console error output only. Change-Id: Icdfd1f9162bb5e557c711b6363b73ef55fbc272d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/328490 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* chip: it83xx: it8320 compatibilityDino Li2016-02-182-0/+3
| | | | | | | | | | | | | | | | | | To ensure it8320's compatibility on the LPC platform, we need to disable SPI slave interface (default enabled) so that LPC module will function normally. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=LPC module of it8320 works normally. Change-Id: I259651b32f41ebae498e13bf07ebb68e5e520058 Reviewed-on: https://chromium-review.googlesource.com/328142 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* kunimitsu: hibernate: enable PseudoG3 support at board levelKevin K Wong2016-02-1811-55/+52
| | | | | | | | | | | | | | this is to move the existing code from chipset level to board level since PseudoG3 is a board feature that required specific hardware. BUG=none BRANCH=glados TEST=use hibernate command to enter PseudoG3 Change-Id: I309ef89e0ff7057ce46c634baa9791731a771984 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/327677 Reviewed-by: Shawn N <shawnn@chromium.org>
* gaia, mediatek, rockchip, tegra: No more disabling key scanning in power filesDouglas Anderson2016-02-184-25/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In http://crosreview.com/28402 code was added to power/gaia.c that disabled keyboard scanning if the power button was pressed. The purpose, according to that change, was to prevent accidental reboots by pressing the power button together with another key that wasn't the "Refresh" key (specifically: LCtrl, Tab, Reload, t, [, ], y, Dim Screen and Mute). At the time the original code was added, there was already code in the power button interrupt handler to accomplish the same purpose: see commit 29d25d807c18 ("Keyboard scan must stop driving columns when power button is pressed."). It's unclear if the code in the interrupt handler didn't work or if there was some other bug with it. ...or if perhaps the changes in "gaia/power.c" weren't actually needed and the important part of the original change was the mutex added to the scanning task. In any case, current testing indicates that the code in power/gaia.c, power/rockchip.c, and power/tegra.c isn't needed anymore. I ran through the test sequence described in the original CL on my veyron_jerry and I don't see any accidental reboots. It's also instructive to note that only ARM boards (all presumably copied from gaia) have this extra code. Presumably if the code was actually needed then x86 boards would also need it. In any case, let's remove it. It's suspected that there's some crazy race where the disable in power/rockchip.c is overriding the enable in the main power key handling code and leaving the keyboard disabled. BRANCH=None BUG=chrome-os-partner:48470 TEST=Same test as CL:28402 Change-Id: I6d21167ce3d773c9616abd4a728247a1934b96d6 Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327843 Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit dfae7e7ad45f4ce0e8f820caaa05a8754bba0250) Reviewed-on: https://chromium-review.googlesource.com/328013
* chip: it83xx: disable fan control timer if all fans are offDino Li2016-02-171-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | Before the change was made, the fan control timer keeps running even all of the fans are off. reproduce the problem: 1. fanset 3333 2. fanset 0 fan is disabled but fan control timer keeps running. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. fanset 3333 2. fanset 0 both fan and timer are off. Change-Id: Id38f3a4c64bbb36e8b32baefd285dbb0bf14e47e Reviewed-on: https://chromium-review.googlesource.com/327870 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* config: it83xx: remove "CONFIG_IT83XX_PECI_WITH_INTERRUPT"Dino Li2016-02-173-15/+0
| | | | | | | | | | | | | | | | IT839x and the new series all support interrupt of PECI, so we remove it. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=make -j buildall Change-Id: Ib126cb418a4ba5ef313ee93948bc2fbb96bc936d Reviewed-on: https://chromium-review.googlesource.com/327643 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* hibernate: Inform PD MCU before calling board hibernate callbackShawn Nematbakhsh2016-02-175-15/+17
| | | | | | | | | | | | | | | | | | board_hibernate() may take alternate actions to place the chip into hibernate, so inform the PD MCU that we're going to hibernate before calling the function. BUG=None TEST=Run 'hibernate' on chell, verify that PD MCU goes to hibernate and wakes when AC is attached. BRANCH=glados Change-Id: I71c12dcb416d54c79ac7d40e9bf430e268071fb2 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327613 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Lars: S0ix/S3 EC power improvementKyoung Kim2016-02-171-2/+2
| | | | | | | | | | | | | | | | | | | | USB2_OTG_ID and USB2_OTG_VBUSSENSE pins were floated due to open drain configuration. Improve EC power and remove power difference between S3 and S0ix. Improve EC power for SOC G3. BRANCH=firmware-glados-7820.B BUG=none TEST=measure EC powers at S3/SOC-G3 and S0ix and check if there are difference Change-Id: I0535be675bc3a3a84214590e8190f1fedae1142c Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/327070 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 6dbad7f06e245bfa99e37326ed0517e81e207ef9) Reviewed-on: https://chromium-review.googlesource.com/327480 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* cr50: add firmware upgrade testVadim Bendebury2016-02-173-2/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extends the test harness with a test verifying firmware upgrade. The test in fact just determines the area available for upgrade, picks the appropriate image and sends it to the device, 1K at a time. The test does not verify that the device in fact switched to the new image, the test succeeds if the device accepts all update messages. BRANCH=none BUG=chrome-os-partner:37774 TEST=verified that all tests still pass: $ ./test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 SUCCESS: AES:ECB common SUCCESS: AES:ECB128 1 SUCCESS: AES:ECB192 1 SUCCESS: AES:ECB256 1 SUCCESS: AES:ECB256 2 SUCCESS: AES:CTR128I 1 SUCCESS: AES:CTR256I 1 SUCCESS: EC-SIGN:NIST-P256:ECDSA New max timeout: 1 s SUCCESS: EC-KEYGEN:NIST-P256 SUCCESS: EC-KEYDERIVE:NIST-P256 SUCCESS: sha1:single:0 SUCCESS: sha256:single:0 SUCCESS: sha1:single:3 SUCCESS: sha256:single:3 SUCCESS: sha256:finish:1 SUCCESS: sha1:finish:3 SUCCESS: sha256:finish:2 -New max timeout: 3 s SUCCESS: RSA-ENC:OAEP:SHA1:768 SUCCESS: RSA-ENC:OAEP:SHA256:768 SUCCESS: RSA-ENC:PKCS1-ES:NONE:768 New max timeout: 49 s SUCCESS: RSA-ENC:PKCS1-ES:NONE:2048 SUCCESS: RSA-SIGN:PKCS1-SSA:SHA1:768 SUCCESS: RSA-SIGN:PKCS1-SSA:SHA256:768 SUCCESS: Firmware upgrade Change-Id: I49052feb8e97a3e281bb20b7fddc359a55e96ae3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327416 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* cr50: upgrade command extensionVadim Bendebury2016-02-173-0/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch suggests a firmware upgrade mechanism implemented through an extended TPM command. The firmware is transmitted in chunks, each chunk accompanied by its checksum (first 32 bits of SHA1) and the base address. The first chunk is of size zero and has the base address set to zero. When the first chunk is received, the command handler determines the destination flash space (A or B), erases it, and returns its base address to the caller, such that the firmware update agent can tell in which of the two spaces it should write the update. The ultimate verification happens after the device is reset - the integrity and authentity of the firmware upgrade is verified at that point, the new firmware will not be started unless it is properly signed. BRANCH=none BUG=chrome-os-partner:37754 TEST=with all patches applied it is possible to upgrade firmware in both spaces A and B. Change-Id: I6aedc587ec630d65ba81000496f372c9044959a0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327415 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: allow board to provide flash configurationVadim Bendebury2016-02-173-9/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | The g chip is used in multiple designs, likely to have different flash memory layout and access permissions. This patch introduces a mechanism which allows the board layer to provide flash configuration information to the flash driver. The flash region which is going to be enabled for write access depends on the area the code is executing from. If running from the bottom half (A), the whole top half should be writeable (this includes both NVRAM area and the B code space). If running from B, the writeable area starts on top of RO and extends to the end of NVRAM. CQ-DEPEND=CL:*248190 BRANCH=none BUG=chrome-os-partner:37754 TEST=with the rest of the patches applied verified that software update can happen in both spaces, A and B. Change-Id: Iab1c1a2766ae9bcfe04ff170c010f180cd1f770f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327412 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Nadim Taha <ntaha@chromium.org>
* cr50: improve flash driver error reportingVadim Bendebury2016-02-171-7/+23
| | | | | | | | | | | | | | | | It is difficult to tell what went wrong if a flash operation failed. This patch adds printouts in cases of failure. The extension command console channel is used. BRANCH=none BUG=chrome-os-partner:37754 TEST=observed error messages reported while debugging firmware update code. Change-Id: I73d509ac5088249e8d34e32e760f3d2f063c91cd Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327411 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* wheatley / nuc: Modified the internal ref voltage of ADC to 2.816VMulin Chao2016-02-172-3/+3
| | | | | | | | | | | | | | | | | | | In order to prevent the influence of the deviation of AVCC during ADC conversion, the internal reference voltage (Vref) of ADC is fixed to 2.816V even it derives from AVCC. Modified sources: 1. wheatley/board.c: Modified max adc voltage of ADC to 28.160V. 2. adc_chip.h: Modified internal ref voltage of ADC to 2.816V. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ib514f4bdc114802870eb3c77c650e18c05eb9617 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/327046 Reviewed-by: Shawn N <shawnn@chromium.org>
* Lars: Power LED to blink in S0iX state.Divagar Mohandass2016-02-161-1/+1
| | | | | | | | | | | | | | | | | | In S0ix state, power LED remains is same state as S0. This change will make the power LED to blink in S0iX state. BUG=none BRANCH=glados TEST=Build/Flash and verify LED status during S0ix and S3. Change-Id: Iecb1ca1cdf0ebb6d5b10b55bdc4912fd987bb677 Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-on: https://chromium-review.googlesource.com/327361 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shobhit Srivastava <shobhit.srivastava@intel.com> Tested-by: Shobhit Srivastava <shobhit.srivastava@intel.com> (cherry picked from commit b037f892020b9fd1a115f144dbfd6aac09896aa0) Reviewed-on: https://chromium-review.googlesource.com/327441
* lucid: add battery cutoff functionalityMary Ruthven2016-02-161-0/+2
| | | | | | | | | | | | | | Add the config option to enable battery cutoff functionality. BUG=none BRANCH=none TEST=use console command to cutoff battery, and verify it wakes up when the adapter is plugged in. Change-Id: I50ceeb2efc5dbd7843fbe8c1cef489a32848817f Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327249 Reviewed-by: Shawn N <shawnn@chromium.org>
* Lars: Enable S0ix.Divagar Mohandass2016-02-142-2/+4
| | | | | | | | | | | | | | | | | | | | | This change will enable S0ix related state transition logic for Lars platform. BUG=None BRANCH=glados TEST=In OS shell, run 'echo freeze > /sys/power/state' command to tigger S0ix. Change-Id: I15d273f8d9b24c24155437dae5ff673909eee50c Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-on: https://chromium-review.googlesource.com/324740 Tested-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> (cherry picked from commit b96aa25174e50f61ae4bede5bc6b078bffef2a7e) Reviewed-on: https://chromium-review.googlesource.com/326621 Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* cr50: modify mpsse to work with the new deviceVadim Bendebury2016-02-132-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The ultra debug board uses a different FTDI chip (vid:did 0403:6010), which has two ports. The SPI interface on this chip is hooked up to the second port, but the code indiscriminately uses the first port when trying to open the SPI channel, on all devices known to it. Adding a new field in the supported_devices table allows to keep default behavior, but use port B (the second port) when required. Also, fix printout formatting problem. BRANCH=none BUG=chrome-os-partner:37754 TEST=tpmtest succeeds with the new board Change-Id: I01f7937444c8df61d7439a66d9da89fb2cac5372 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327232 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: improve loader logic to consider build timestamp as wellVadim Bendebury2016-02-121-16/+13
| | | | | | | | | | | | | | | | | | | When deciding which of the two images to start, A or B - consider the image timestamp if everything else is equal. The later image should take precedence. Also, simplify the existing logic, and consider image A to be 'newer' if both copies are the same otherwise. BRANCH=none BUG=chrome-os-partner:37754 TEST=with the rest of the patches applied, verified that the newer image of the two gets started Change-Id: I2c7a50ecfc8d254498c8e96f8651b8d53005897c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327414 Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: write protect area where the code jumps toVadim Bendebury2016-02-121-1/+2
| | | | | | | | | | | | | | | The launcher should explicitly disable writes to the code space where the loaded code is going to be running from. BRANCH=None BUG=chrome-os-partner:37554 TEST=with the rest of the patches applied firmware updates work as expected. Change-Id: I744f7016e4427188f53e8fa3302e8c06cf836e2e Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327413 Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: test: consolidate test exceptionsVadim Bendebury2016-02-116-63/+53
| | | | | | | | | | | | | | | | | | | | | | There is no point in defining tpm test exception classes per test type, one common class is enough, especially if the source module of the exception is reported. BRANCH=none BUG=none TEST=tried running the test without the USB FTDI cable plugged in, got the following error message: $ ./test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Error in tpmtest.py:54: Failed to connect $ Change-Id: I5642aa70c8a581099887b58e3a436d7f8d7608a1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327300 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* Add bionic compatibilityAnatol Pomazau2016-02-102-1/+2
| | | | | | | | | | | | | | TEST=Build ectool for Android and run it BUG=None BRANCH=master Signed-off-by: Anatol Pomazau <anatol@google.com> Change-Id: I5f148adfc24591523a7d8c50817c8095072071c3 Reviewed-on: https://chromium-review.googlesource.com/327220 Commit-Ready: Anatol Pomazau <anatol@google.com> Tested-by: Anatol Pomazau <anatol@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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