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* UnitTest: Create battery mock for tcpmv2_complianceDenis Brockus2021-01-072-0/+212
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I1b06d512b3b869a300c981c4dd6bda54a236f342 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2614773 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* Revert "TCPMv2: Decrease Low Power Mode debounce delay to 10 ms"Keith Short2021-01-071-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 5ff18dfd6ab67df2e62c6af9f20ed472808de707. Reason for revert: b:176986511 Volteer family devices need at least 75ms debounce to detect attachment of SNK devices. Original change's description: > TCPMv2: Decrease Low Power Mode debounce delay to 10 ms > > This patch decreases PD_LPM_DEBOUNCE to 10 ms. With current > 100 ms delay ANX7447 can't go to Low Power Mode due to silicon > bug (b:77544959). When DRP mode is enabled ANX7447 triggers alert > every 39.7 ms. Checking what caused an alert involves I2C > transaction which changes timeout after which TCPC goes to Low > Power Mode to get_time().val + PD_LPM_DEBOUNCE_US. As a result it > is not possible to put TCPC to LPM which is necessary to work > properly (b:149761477) > > Original value for PD_LPM_DEBOUNCE_US was 10 ms, introduced > in CL:1119255. This value is still used in TCPMv1. > For TCPMv2, PD_LPM_DEBOUNCE_US was changed to 100 ms in CL:2126078. > It is unclear why this value was changed. Review discussion and bug > b:149772936 don't mention why we needed to change that, so we change > it back to 10 ms for consistency with TCPMv1. > > Issue was found when running EC ToT with TCPMv2 enabled on bobba board. > > BUG=b:161775827, b:77544959, b:149761477 > BRANCH=none > TEST=Flash EC ToT on octopus board with ANX7447 (eg. bobba). > Make sure that DRP mode is enabled. Connect charger to port > with ANX7447 chip. Make sure that EC can connect with charger. > > Signed-off-by: Patryk Duda <pdk@semihalf.com> > Change-Id: Ia08818378a1fca424d392b4699f9c4adc460bfb5 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606235 > Reviewed-by: Edward Hill <ecgh@chromium.org> Bug: b:161775827 Bug: b:77544959 Bug: b:149761477 Change-Id: I882c077915b67b53acc73e2941ead33baabe9b5f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615118 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org>
* TCPMv2: Update exiting Thunderbolt mode SOPAyushee Shah2021-01-071-1/+1
| | | | | | | | | | | | | | | | On receiving the ack for exiting thunderbolt mode SOP, call the tbt_exit_done() function instead of only clearing TBT_FLAG_RETRY_DONE flag. BUG=b:173459141 BRANCH=none TEST=Able to enter and exit AP driven Thunderbolt mode Signed-off-by: Ayushee Shah <ayushee.shah@intel.com> Change-Id: Icc941beec027f808aa2eafd5190c977640b7599e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613727 Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* version: Rename version.h to cros_version.hYuval Peress2021-01-0719-18/+18
| | | | | | | | | | | | | | | This change simply moves the include/version.h file over to avoid a naming collision with zephyr's version.h. BRANCH=none BUG=b:167392037 TEST=make buildall -j Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ib41b3c21817d5f81e713d3b550bc46a0d1c55cf8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612772 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* usb_pd: correct PD control flag bit shiftingAyushee Shah2021-01-071-5/+9
| | | | | | | | | | | | | | | | PD control flag returned to host doesn't have correct bit shifting, this causes enumeration failure of TBT devices using MBR cable. Hence, corrected PD control flag bit shifting BUG=b:176604391 BRANCH=none TEST=Test with MBR cable and enumeration is successful. make buildall -j Signed-off-by: Ayushee Shah <ayushee.shah@intel.com> Change-Id: Ica3c71b00e435c5ba417717baf22fc6dc26f9a92 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613904 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* BB retimer: Set UFP mode of BB retimerAyushee2021-01-077-54/+142
| | | | | | | | | | | | | | | | | | | | | This CL enables getting the enter mode information received from DFP and sets the following BB retimer bits accordingly. Bit 2: RE_TIMER_DRIVER Bit 18: CABLE_TYPE Bit 19: VPRO_DOCK_DETECTED Bit 20: TBT_ACTIVE_LINK_TRAINING Bit 22: ACTIVE/PASSIVE Bits 27-25: TBT Cable speed Bits 29-28: TBT_GEN_SUPPORT BUG=b:157163664 BRANCH=None TEST=Tested with volteer as UFP, able to set the retimer bits Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: I661aa4630b42fbaa136ff3855c4f70e3dee61546 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2382634 Reviewed-by: Keith Short <keithshort@chromium.org>
* Metaknight: Remove USB C1Yu-An Chen2021-01-074-46/+14
| | | | | | | | | | | | | | | | | | | | | | Add DB_LTE_HDMI in dedede fw_config_db Remove metaknight USB C1 port Remove C1 PD task and PD int task Remove OCPC BUG=b:176275423 BRANCH=main TEST=make BOARD=metaknight TEST=make BOARD=metaknight_legacy TEST=make buildall -j4 TEST=check EC console ,EC will not init DB raa489000. Signed-off-by: yu-an.chen@quanta.corp-partner.google.com Change-Id: Ibd86ee852ba870a95e5b552588c7f81ce77a122d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2603095 Tested-by: Yu-An Chen <yu-an.chen@quanta.corp-partner.google.com> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org> Auto-Submit: Yu-An Chen <yu-an.chen@quanta.corp-partner.google.com>
* zephyr: remove guard to call of lpc_s3_resume_clear_masksJack Rosenthal2021-01-071-6/+1
| | | | | | | | | | | | | | This function is shimmed now, we can take away the guard. BUG=b:172678200 BRANCH=none TEST=power on volteer Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I7589b3485930e8d40966e9e71434b98648018872 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615130 Commit-Queue: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* ctn730: Resend i2c on any errorDaisuke Nojiri2021-01-071-2/+2
| | | | | | | | | | | | | | | | | | Currently, ctn730 driver resends i2c frame only if EC_ERROR_BUSY is returned. The i2c error in this case varies chip to chip. NPCX i2c returns EC_ERROR_UNKNOWN, for example. Instead of expecting a specific error, this patch makes CTN730 driver resend I2C on any error. BUG=b:176725734 BRANCH=None TEST=On CoachZ. Verified 'Failed to read/write' disappeared. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I0b461935810aa253c8399cc2a6f9573a4aab123d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2611915 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ish: enable GPIO wake from low power stateLeifu Zhao2021-01-072-0/+8
| | | | | | | | | | | | | | | | | Enable GPIO wake from low power state for ish 5.4 on tgl rvp. BUG=b:176670515 BRANCH=none TEST=Sensor GPIO interurpt can successfully wake up ish. Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: Id3eb997ad8dded95c154250e64cd3a5b287bb3d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607953 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Jett Rink <jettrink@chromium.org> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* guybrush: Temp sensor configurationRob Barnes2021-01-072-3/+137
| | | | | | | | | | | | | | Configuration for temp and thermal. ADC channels also configured. BUG=b:175408269 TEST=Build BRANCH=None Change-Id: I63aae0366ccb0251163b0660cb47797fe004e68e Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2586043 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Move tcpic.h header into include/driverSimon Glass2021-01-0772-71/+71
| | | | | | | | | | | | | | | | | | This header cannot currently be accessed by Zephyr since it is in a driver directory, not an include directory. This header has quite a bit of public stuff in it, so it seems reasonable to consider everything public. Move the header file and update all users. BUG=b:175434113 BRANCH=none TEST=make buildall -j30 build volteer on zephyr Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: Ibba37f47a06783fafb5095f853f2a68d92b6df87 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607745
* flash_it83xx: implement --noverifyTing Shen2021-01-072-3/+16
| | | | | | | | | | | | | | | | | | | | Support --noverify to speed up flashing. Note that --noverify is enabled by default in flash_ec script, so people need to add --verify explicitly to back to the old behavior. This reduces ~20% time on my machine (7m45s -> 5m50s). BUG=None TEST=manually, Verify the line "Verify 1048576 bytes at 0x00000000" disappeared. BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ia9e15a2f7221bd0af6da55de0bf90938a7afedeb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612688 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* Create a public header for isl9241Simon Glass2021-01-073-27/+40
| | | | | | | | | | | | | | | | | Add a separate public header for this chip so we can include it from Zephyr. Update the charger file to use that header, so it builds on Zephyr. BUG=b:175434113 BRANCH=none TEST=make BOARD=volteer -j30 With a zephyr-chrome CL, build volteer on zephyr Change-Id: I562177e2259931730b7dae4d8e43edd5ea96deb7 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2611893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* Create public headers for a few PPC/TCPM driversSimon Glass2021-01-0710-71/+136
| | | | | | | | | | | | | | | | | | | | | | At present boards includes the private header of some of the drivers. This is not ideal but it works. For Zephyr we don't really want to access headers in private driver directories. Instead, create public headers for the five drivers needed by the Zephyr volteer build. For now, include the public header in the private header (the one included by the EC code), so that fewer code changes are required. BUG=b:175434113 BRANCH=none TEST=make buildall -j30 (way too verbose to see what is happening) build volteer on zephyr Change-Id: I5b810f53cdf545a885f3977849f9f2ca1d04d60a Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607506 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* Zephyr: Add Kconfigs for RUNTIME_CONFIGSimon Glass2021-01-072-1/+51
| | | | | | | | | | | | | | | | Add support for USB_PD_TCPC_RUNTIME_CONFIG and USB_MUX_RUNTIME_CONFIG so that we get the correct type for tcpc_config[] and usb_mux[]. BUG=b:175434113 BRANCH=none TEST=make BOARD=volteer -j30 With a zephyr-chrome CL, build volteer on zephyr Signed-off-by: Simon Glass <sjg@chromium.org> Cq-Depend: chromium:2607401 Change-Id: Ic4c982f5d697cd6b61d83f2f12657220a5325094 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607508 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Boten: Add raa489000_hibernate() to reduce G3 power consumptionreno.wang2021-01-071-0/+9
| | | | | | | | | | | | | | | 1. Boten adopt RAA48900 charge/tcpc. 2. Add raa489000_hibernate() function to reduce power power consumption when system enter G3 state. BUG=b:175361186 BRANCH=dedede TEST=make buildall, the Boten's power consumption in G3 can be reduced. Signed-off-by: reno.wang <reno.wang@lcfc.corp-partner.google.com> Change-Id: Idc6f0447610e5e01220570b074ebf732e8f237aa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2610536 Reviewed-by: Diana Z <dzigterman@chromium.org>
* it83xx/system: introduce GPG1 reset EC featureDino Li2021-01-072-0/+18
| | | | | | | | | | | | | | | | | This CL added option of CONFIG_IT83XX_HARD_RESET_BY_GPG1. If we enabled the option, EC will assert GPG1 pin to reset itself instead of triggering an internal reset while receiving a reset request. BUG=b:173075595 BRANCH=none TEST=Enable CONFIG_IT83XX_HARD_RESET_BY_GPG1 and check if GPG1 goes high while receiving reset command. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I930424c374dcbd742b8ecca7a1fa720699d42bb6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612233 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* copano: Config the G-sensor settingJacky Wang2021-01-074-20/+20
| | | | | | | | | | | | | | | | | | 1. Base on schematics, modify the motion sensor related setting to BMI160. 2. Modify base rotation matrix depend on schematics. BUG=b:176393206 BRANCH=firmware-volteer-13672.B TEST=make BOARD=copano 1. Using "ectool motionsense" check x/y/z value. 2. Using "ectool motionsense lid_angle" check angle. Signed-off-by: Jacky Wang <jacky5_wang@pegatron.corp-partner.google.com> Change-Id: If82879f16e45d780c1fc8878d6a8f94dddaf0e3a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607035 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Michael5 Chen <michael5_chen1@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
* Metaknight: Modify pen charge behaviorYu-An Chen2021-01-071-3/+11
| | | | | | | | | | | | | | | | | | Disable pen charge when system in S5/G3. BUG=b:176202016 BRANCH=master TEST=make BOARD=metaknight TEST=make BOARD=metaknight_legacy TEST=check EC console ,works as expected. Signed-off-by: yu-an.chen@quanta.corp-partner.google.com Change-Id: I156961a54364f4e04b71e269218ca37a1bf4520a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600808 Tested-by: Yu-An Chen <yu-an.chen@quanta.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Yu-An Chen <yu-an.chen@quanta.corp-partner.google.com>
* TCPMv2: Update BIST commentsAbe Levkoy2021-01-061-17/+19
| | | | | | | | | | | | | Correctly cite PD 3.0 spec. BUG=none TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I26de0d34e99291d5320051ff47f0fc7c5d84b4b3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2545666 Reviewed-by: Diana Z <dzigterman@chromium.org>
* TCPMv2: Remove PE_BIST_RX stateAbe Levkoy2021-01-063-53/+10
| | | | | | | | | | | | | | Nothing uses this, and anyway, the EC doesn't have the means to evaluate the results of a BIST Carrier Mode test that it initiates. BUG=none TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I8aa0d97c81422689de4ca165cb2c0c34c324f6a2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2602719 Reviewed-by: Diana Z <dzigterman@chromium.org>
* Split out charger information into a new fileSimon Glass2021-01-063-10/+19
| | | | | | | | | | | | | | | | The Zephyr build needs this information but cannot use the whole baseboard.c file. It is pretty big anyway, so let's move the charger info into a separate file. BUG=b:175434113 BRANCH=none TEST=make BOARD=volteer -j30 With a zephyr-chrome CL, build volteer on zephyr Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: Ib91ae850358e5045e6530e2308a49835aee6a3f5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607507 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Add Kconfig for USB PIDSimon Glass2021-01-062-0/+16
| | | | | | | | | | | | | | | | This is the USB product ID and is needed for reporting identity information to connected USB devices. Add a Kconfig for it. BUG=b:175434113 BRANCH=none TEST=with zephyr-chrome CL, build on volteer with full EC usb_pd_policy.c Cq-Depend: chromium:2607398 Change-Id: I71aa1b9110dbe526a31555b16723e31e57c314e9 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607505 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org>
* pompom: change panel blacklight PWM frequencyjohnwc_yeh2021-01-061-1/+1
| | | | | | | | | | | | | | | | | | Noise is related with LCD Panel and Brightness PWM. Change panel blacklight PWM frequency to 200Hz. BUG=b:175795667 BRANCH=none TEST=Boot into OS can not hear the noise. Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com> Change-Id: Iac1789dcc58beb9f4fa3eb006f9b4ff39d0c9a71 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607220 Tested-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Reviewed-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Reviewed-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* TCPMv2: Compliance Unit Test - allow rx with data to have timeoutDenis Brockus2021-01-064-5/+12
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Iafbb0dd23a72ef32a1b3100fdfdeaf57c58b51f8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613249 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* TCPMv2: Compliance Unit Test - Default TRY.SRC to OFFDenis Brockus2021-01-061-0/+7
| | | | | | | | | | | | | | | | | If a test specifically needs to test TRY.SRC, it should re-enable this to TRY_SRC_NO_OVERRIDE BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Id71e4e0cf5f96df3e005a58818b218def6ba31c5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613248 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* TCPMv2: Compliance Unit Test - add display for EXT messagesDenis Brockus2021-01-061-30/+56
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I6d1f1ea59c07fa36d5817b9d3a8615ac633964d4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613247 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* TCPMv2: Unit Test - add filename to TEST_ failing outputDenis Brockus2021-01-061-7/+10
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I2cc35425de4b29c7f5b958428a00efdf1e31e004 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613246 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* zephyr: Update Kconfig for the remaining console commandsSimon Glass2021-01-061-9/+34
| | | | | | | | | | | | | | | | Use the same format for these existing commands and add some help so that it is clear what they do. BUG=b:176449230 BRANCH=none TEST=ninja -C /tmp/z/vol/build-ro menuconfig Check that each command looks correct Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I146e22f05349d7b2d803ef7879c72420bdc62ce4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607456 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr: Update USB-C Kconfig for claritySimon Glass2021-01-061-30/+43
| | | | | | | | | | | | | | | | | | Two of the options have a lot of dependencies, so use menuconfig for these. Also move dependencies together in the file to avoid confusion. Drop the 'Enable' language since it just slows down reading of the available options. BUG=b:176449230 BRANCH=none TEST=ninja -C /tmp/z/vol/build-ro menuconfig Check the options read a bit better Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I8629ffbe22a1b0d35114b625b01559f167b8b45b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2605814 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Use clearer prompts for config optionsSimon Glass2021-01-061-31/+70
| | | | | | | | | | | | | | | | | | | | | | | At present the useless word 'Enable' appears in lots of the options, making it harder to read what is actually important, the thing being enabled. Also some options have pretty poor help, which does not set a good example for the future. Tidy up these things. BUG=b:176449230 BRANCH=none TEST=ninja -C /tmp/z/vol/build-ro menuconfig Check the options read a bit better Change-Id: I3f4c2d21a52e9776b85c27a72701cf3a7e584728 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606578 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: Make HAS_TASK_HOSTCMD a Kconfig optionSimon Glass2021-01-063-12/+22
| | | | | | | | | | | | | | | | | | | | This option is implied so we may as well create it. Set it to be visible (and automatically enabled) only if PLATFORM_EC_HOSTCMD is enabled. This mostly mimics the current behaviour. Also select the hostcmd task automatically if PLATFORM_EC_HOSTCMD is enabled, since that feature cannot work without the task. If PLATFORM_EC_HOSTCMD is not enabled there is no need for the task. BUG=b:176449230 BRANCH=none TEST=ninja -C /tmp/z/vol/build-ro menuconfig Check the operation of HAS_TASK_HOSTCMD and PLATFORM_EC_HOSTCMD Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I837c6b30bfc9746a17a697b9ee94a7870a01fb56 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606577 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Connect HAS_TASK_CHARGER and PLATFORM_EC_BATTERYSimon Glass2021-01-062-0/+2
| | | | | | | | | | | | | | | | | | | | | These options are linked in that we cannot have one without the other. Select the charger task automatically if PLATFORM_EC_BATTERY is enabled, since that feature cannot work without the task. If PLATFORM_EC_BATTERY is not enabled there is no need for the task. BUG=b:176449230 BRANCH=none TEST=ninja -C /tmp/z/vol/build-ro menuconfig Check the operation of HAS_TASK_CHARGER and PLATFORM_EC_BATTERY Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I14ada8716053649ac13ea12a7b06c2ae1702df42 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606576 Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Connect HAS_TASK_POWERBTN, PLATFORM_EC_POWER_BUTTONSimon Glass2021-01-062-1/+3
| | | | | | | | | | | | | | | | | | | | | These options are linked in that we cannot have one without the other. Select the powerbtn task automatically if PLATFORM_EC_POWER_BUTTON is enabled, since that feature cannot work without the task. If PLATFORM_EC_POWER_BUTTON is not enabled there is no need for the task. BUG=b:176449230 BRANCH=none TEST=ninja -C /tmp/z/vol/build-ro menuconfig Check the operation of HAS_TASK_POWERBTN and PLATFORM_EC_POWER_BUTTON Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I3e6bb2dccb58009ad4f8c4931dbcb43665327a8b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606575 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: Make HAS_TASK_KEYSCAN a Kconfig optionSimon Glass2021-01-063-9/+28
| | | | | | | | | | | | | | | | | | | | | This option is implied so we may as well create it. Set it to be visible (and automatically enabled) only if PLATFORM_EC_KEYBOARD is enabled. This mostly mimics the current behaviour. Also select the keyproto task automatically if PLATFORM_EC_KEYBOARD_PROTOCOL_8042 is enabled, since that feature cannot work without the task. If PLATFORM_EC_KEYBOARD_PROTOCOL_8042 is not enabled there is no need for the task. BUG=b:176449230 BRANCH=none TEST=ninja -C /tmp/z/vol/build-ro menuconfig Check the operation of HAS_TASK_KEYSCAN and PLATFORM_EC_KEYBOARD Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I576f2ee3560a307e00d11bc6b8b6c04acb81dd24 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606574 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Make HAS_TASK_CHIPSET a Kconfig optionSimon Glass2021-01-063-10/+28
| | | | | | | | | | | | | | | | This option is implied so we may as well create it. Set it to be visible (and automatically enabled) only if PLATFORM_EC_POWERSEQ is enabled. This mostly mimics the current behaviour. BUG=b:176449230 BRANCH=none TEST=ninja -C /tmp/z/vol/build-ro menuconfig Check the operation of HAS_TASK_CHIPSET and PLATFORM_EC_POWERSEQ Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I7dc698c15fa65eb16ec40724a06b67d7e4ddc27d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606573 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: add a fake shared memory implementation for posix-ecJack Rosenthal2021-01-063-1/+18
| | | | | | | | | | | | | | | | | | | | | | CL:2575207 was not tested against posix-ec and caused build issues. posix-ec does not have the _image_ram_end symbol available. This adds a new configuration for a fake 1MB shared memory option, and enables it for posix architecture by default. Note that if this CL (or an alternative fix) cannot be landed in a timely fashion, CL:2575207 and any CLs which depend on it should be reverted so we can enable the CQ again and stop stepping on our own toes. BUG=b:176828988 BRANCH=none TEST=run zephyr-chrome firmware_builder.py Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I1d828f480c6a5da0b162a124c8a5a62ae8afb444 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2611985 Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr: usbc: disable by default for devices without a batteryJack Rosenthal2021-01-061-1/+1
| | | | | | | | | | | | | | | | | | | | For devices without a battery (e.g., posix-ec), this code has compile issues. Note that it's still possible to have devices with USB-C but no battery (e.g., Chromeboxes), so this is not a strict "depends on". If we make Chromeboxes in the future with Zephyr then we can either set PLATFORM_EC_USBC manually or re-evaluate (e.g., "default y if CHROMEBOX") BUG=b:176828988 BRANCH=none TEST=less compile errors for posix-ec Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I0fe76199bd75b93c907fd79f571f5951c350b06f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2611984 Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr: disable flash storageJack Rosenthal2021-01-061-1/+1
| | | | | | | | | | | | | | This code fails to compile (see b/176828988). Disable by default until this code can be compiled. BUG=b:176828988 BRANCH=none TEST=less compile errors Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I051a7491d88194a212ece0843b7b76611998886c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2611823 Reviewed-by: Yuval Peress <peress@chromium.org>
* ec_commands: Add chipset_{reset,shutdown}_reasonYu-Ping Wu2021-01-062-69/+68
| | | | | | | | | | | | | | | Move enums chipset_{reset,shutdown}_reason from chipset.h to ec_commands.h for coreboot to use. BUG=b:174443398 TEST=emerge-asurada chromeos-ec TEST=make buildall -j BRANCH=none Change-Id: I8939ab86b4277170139e79f6806d9e70ce57964f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607150 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* asurada: disable FRS due to syv682bx hardware faultEric Yilun Lin2021-01-061-2/+0
| | | | | | | | | | | | | | | | | | The issue is that, when a port sink for 5V, and triggers FRS, and the port would fail to source and the PPC is in a weird state and unable to recover until a hard reset. This CL disable the feature temporarily until we have a H/W fix. BUG=b:176876036 TEST=make BOARD=asurada BRANCH=none Change-Id: Ieed93c5c1fc4acfbe2f9ac135cf90ab459ae8cdd Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612241 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* asurada: increase i2c freq to 400KhzEric Yilun Lin2021-01-061-3/+3
| | | | | | | | | | | | | | This CL increase the i2c freq to 400Khz to finish the i2c task, and let it81202 enter the doze state faster. BUG=b:173490375 TEST=ensure S3 power consumption drop to 5mw BRANCH=none Change-Id: Iee12f61075214b7f585a9b7d2c2ad6f64666d4f2 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607967 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* hayato: enable lid sensor interruptTing Shen2021-01-062-1/+11
| | | | | | | | | | | | | | | | | | | | | After HW fix implemented, we can finally enable lid accel interrupt. This CL changes the hard-coded force mode mask to a runtime computed value, such that polling mode still works on rev 1 boards, and enable interrupt mode on rev 2+ boards. BUG=b:157974230 TEST=Manually, 1) On rev2 board, verify lis2dw12_interrupt triggered. 2) On rev1 board, verify lid accel still works. BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ic64baed39db785c13e30a335c68d887dd3d3707d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2610744 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* adlrvpm: add Alderlake-M RVP supportSooraj Govindan2021-01-0610-1/+72
| | | | | | | | | | | | | | | | | | | | | | Following features are enabled and verified. 1. Power sequencing 2. Host communication 3. USB TYPE-C - TCPC over PD AIC 4. H1 Close Case Debug 5. LED 6. Keyboard BRANCH=None BUG=b:169551130 TEST=Build, flash and boot the Alderlake RVP platform to OS make BOARD=adlrvpm_ite -j; sudo util/flash_ec --board=adlrvpm_ite --image=<path> Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: I3ee12a0875cb6310c3b5767cab90f17f9646e02c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2584553 Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* waddledoo: Check Type-C interrupt lines at initAseda Aboagye2021-01-061-11/+4
| | | | | | | | | | | | | | | | | | After a sysjump, it could be possible that the Type-C interrupt lines are asserted. This commit simply has the EC check the interrupt lines after init and handle them if necessary. BUG=b:143166332 BRANCH=dedede TEST=`make -j BOARD=waddledoo` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I16eef9827ca37cec4b04442a50352795b9652592 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601777 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* waddledee: Check Type-C interrupt lines at initAseda Aboagye2021-01-061-4/+2
| | | | | | | | | | | | | | | | | | After a sysjump, it could be possible that the Type-C interrupt lines are asserted. This commit simply has the EC check the interrupt lines after init and handle them if necessary. BUG=b:143166332 BRANCH=dedede TEST=`make -j BOARD=waddledee` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I5473b1edf533bc1b0f47b8085ae2203d375ef82e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601776 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* sasuke: Rerun USB-C interrupts if still assertedAseda Aboagye2021-01-061-11/+61
| | | | | | | | | | | | | | | | | | | | This commit revises the USB-C interrupt handlers. Sometimes the interrupt line can remain asserted once we've finished handling the interrupt. This commit leverages the work that was done for the other dedede boards to check if the interrupt is still asserted and rerun the interrupt handlers if needed. BUG=b:143166332 BRANCH=dedede TEST=`make -j BOARD=sasuke` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ia3fcd1f38e6de10259276d171128fb5dfa967f47 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601173 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* metaknight: Rerun USB-C interrupts if still setAseda Aboagye2021-01-061-12/+63
| | | | | | | | | | | | | | | | | | | | This commit revises the USB-C interrupt handlers. Sometimes the interrupt line can remain asserted once we've finished handling the interrupt. This commit leverages the work that was done for the other dedede boards to check if the interrupt is still asserted and rerun the interrupt handlers if needed. BUG=b:143166332 BRANCH=dedede TEST=`make -j BOARD=metaknight` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: If6d05594887590ded83aa65146674912da8004d0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601172 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* magolor: Rerun USB-C interrupts if still assertedAseda Aboagye2021-01-061-11/+63
| | | | | | | | | | | | | | | | | | | | This commit revises the USB-C interrupt handlers. Sometimes the interrupt line can remain asserted once we've finished handling the interrupt. This commit leverages the work that was done for the other dedede boards to check if the interrupt is still asserted and rerun the interrupt handlers if needed. BUG=b:143166332 BRANCH=dedede TEST=`make -j BOARD=magolor` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I643e5a94baf38f421d58dc8ab6fc0a409915cdf6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601171 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
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