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* it83xx/nds32: Ensure EXT_IER has been disabled before enabling CPU interruptDino Li2021-09-021-1/+9
| | | | | | | | | | | | | | | | | | This CL read (load operation) an EC's extended interrupt enable register one time after configured. The load operation will ensure chip-level's interrupt has been disabled before enabling CPU interrupt. This CL will also assert failure if EC get interrupt number 0 in ISR. BRANCH=dedede BUG=b:197308582 TEST=No system reboot on storo during the drop test. Change-Id: I593d78626d1e3bb92e5316d1ff78f0ee54711741 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3124483 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* it83xx/riscv: Ensure IER has been disabled before enabling CPU interruptDino Li2021-09-021-1/+9
| | | | | | | | | | | | | | | | | | | | | This CL read EC's IER one time after configured. The load operation will ensure chip-level's interrupt has been disabled before enabling CPU interrupt. BRANCH=asurada, icarus BUG=b:179206540 TEST=create stress test on it8xxx2 evb: - Loop calling task_disable_irq() and task_enable_irq() to enable and disable IRQ 13 (keyboard KSI interrupt). - Toggle KSI continuously. Without the patch, EC will hit IRQ 0 issue in two seconds. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I56bad182bd101d45b00368083b60aabbd9fb8bdb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3139652 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* it83xx/irq: there is no need to configure IER on nds32 core chipDino Li2021-09-011-2/+10
| | | | | | | | | | | | | | | Configure interrupt enable register is redundant on nds32 core chip (IT8320). We just need to configure extended IER. BRANCH=asurada, dedede BUG=b:197308582 TEST=buildall passes, storo and hayato boot. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I8f99f7b937ac98d95b2f50f5be7b461ae3e9a413 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3134888 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* it8xxx2/irq: wait until two equal interrupt values are readDino Li2021-06-081-1/+5
| | | | | | | | | | | | | | | This CL ensures that CPU won't get an IRQ number which is in generating. BRANCH=none BUG=b:179206540, b:189534384 TEST=No panic of unhandled irq. Change-Id: I934fc9ba7aeef520f5e275e8889722c7357c77f1 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2935652 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com>
* it8xxx2: return -1 if EC INT number isn't validDino Li2021-02-041-0/+3
| | | | | | | | | | | | | | | Returns -1 in chip_get_ec_int() to assert unhandled_interrupt in core/riscv-rv32i/init.S if EC interrupt number isn't valid. BUG=b:179206540 BRANCH=none TEST=boot to kernel on hayato. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Id55686ae860404b550b8df707387805b48931b61 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2674686 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Eric Yilun Lin <yllin@chromium.org>
* it83xx: Add support for interrupt and 1.8v selection of GPJ7Dino Li2020-08-041-1/+1
| | | | | | | | | | | | BUG=b:162805450 BRANCH=none TEST=not yet Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ie1525b8a0f67a4700649163b536d09bef9a9671a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335518 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* core/riscv-rv32i: remove return valuesTzung-Bi Shih2020-06-041-9/+3
| | | | | | | | | | | | | | | | | | Return values of chip_enable_irq(), chip_disable_irq(), and chip_clear_pending_irq() are not using. Removes them. BRANCH=none BUG=b:146213943 BUG=b:157521370 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ic7e3e80483f76f35bfe7781ddea48515ab8e3361 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227778 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: move interrupt details to IT83XX specificTzung-Bi Shih2020-05-191-0/+31
| | | | | | | | | | | | | | | | Getting source interrupt number is chip specific. Moves the details to chip implementation. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ia72acf8ec9c09cb329f8d7c92d22476512ffa669 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114951 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* chip/it8xxx1, chip/it8xxx2: GPIO, WUC and IRQ for chip it83201/it83202Ruibin Chang2019-11-221-3/+12
| | | | | | | | | | | | | | | | | | | | GPIO, WUC and IRQ changes for chip it83201/it83202. BRANCH=None BUG=b:133460224 TEST=test GPIO group O, P, Q, R 1.Input: external input 3.3v, GPDR of corresponding pin is 1. (GCR31, GCR32 select 1.8v, validate again for O and P group) 2.Output: GPDR of corresponding pin set 1, measure 3.3v. 3.INT: GPIO_INT input trigger => WU INT (select high, low, rising, falling, both edge trigger mode) => INT => CPU INT 4.Test power-up and down with this CL on ampton. Change-Id: Ifae081c87b3dafcf3f7da84f637ceaf64a5ed536 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1675704 Reviewed-by: Jett Rink <jettrink@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core:RISC-V / chip:IT83202Dino Li2019-06-111-5/+13
| | | | | | | | | | | | | | | | The IT83202 is an embedded controller with RISC-V core. It supports maximum ram size to 256KB and internal flash to 1MB. BUG=none BRANCH=none TEST=EC boots and test console commands (eg: taskinfo, version, sysjump...) on it83202 EVB. Change-Id: I424c0d2878beb941c816363b5c7a3f57fda9fd13 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1588300 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-261-2/+2
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* it83xx: IT8320 DX version compatibilityDino Li2018-07-111-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [espi]: The supported maximum frequency of slave is adjustable and we set it at 66MHz at initialization (the same as Bx version). [gpio]: All GPIOs support interrupt on rising, falling, and either edge. More GPIOs support 1.8v input. [irq]: Enable newly added interrupts. [registers]: Remove unused declaration. [system]: Watchdog reset supports resetting the full EC domain function (include write protect setting). BUG=none BRANCH=none TEST=[espi]: Ensure the eSPI frequency is able to work at 50 MHz on small core CPU. [gpio]: The settings of input voltage 1.8v selection and both edge interrupt registers are matched to the declarations of GPIO signal in gpio.inc. [system]: The console command "reboot hard" is able to unprotected the flash. (testing failed) Change-Id: I053d8a59a9e90d28e2f2c9b79675ea84425f4959 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1113166 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx: Complete EC interrupt liststabilize-8337.BDino Li2016-05-161-6/+6
| | | | | | | | | | | | | | | | | | There are more EC interrupts available. Also, update interrupts that should be reserved. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Use 'task_enable_irq()' to enable new-added interrupts and corresponding bit of interrupt enable register are set properly. Change-Id: If1aecec7e208782b4580e33efb968095f30794fe Reviewed-on: https://chromium-review.googlesource.com/344822 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip: it83xx: add USBPD moduleDino Li2016-04-181-1/+1
| | | | | | | | | | | | | | | | | | | Add USBPD module for it8320 emulation board BRANCH=none BUG=none TEST=manual plug zinger adapter, connect uart console and type commands: pd 1 dev [20|12|5] pd 1 charger pd 1 swap power and check PD states Change-Id: I9ca1822deeb4b4dce1279a09490ed4175890cf3a Signed-off-by: Leon-Lee <leon.lee@ite.com.tw> Signed-off-by: Dino Li <dino.li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/326230 Reviewed-by: Shawn N <shawnn@chromium.org>
* it8380dev: fix irq, jtag and systemDino Li2015-11-011-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | [irq] 1. The chip_init_irqs() function clears all IERx and EXT_IERx registers. [jtag] 2. Enable debug mode through SMBus. [system] 3. remove console_force_enabled functions. 4. implement __no_hibernate, scratchpad and nvcontext functions. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=chrome-os-partner:23575 TEST=1. IERx and EXT_IERx registers are all cleared after chip_init_irqs(). 2. console command "scratchpad" and "hibernate". 3. bram bank0 index 0x10 ~ 0x1F (16 bytes) for system_get_vbnvcontext() and system_set_vbnvcontext functions. Change-Id: If044d50c69ae80b013ab646a3a6931cec7560ec4 Reviewed-on: https://chromium-review.googlesource.com/309390 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix hw timer and related function.Dino Li2015-10-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [chip config] 1. No hardware specific udelay(). 2. Enable watchdog. [watchdog] 3. Watchdog period is "CONFIG_WATCHDOG_PERIOD_MS" of config.h. 4. Watchdog auxiliary timer period is "CONFIG_AUX_TIMER_PERIOD_MS". [task and irq] 5. Write 1 to clear interrupt pending status, no |. 6. A global variable for store interrupt number of software interrupt. [uart] 7. Always reset UART module before config it. [hwtimer] 8. Use more external timers for HW timer module. [task] 9. Fix task profiling. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=[watchdog] 1. console "waitms 1100", only pre-watchdog warning message. 2. console "waitms 1600", warning message and watchdog reset. [hwtimer] 3. console commands "gettime", "timerinfo", and "forcetime". 4. enable hook debug and there is no delayed by more than 10% warning message over 48 hours. 5. There is no watchdog reset too. [task] 6. console 'taskinfo' Task Ready Name Events Time (s) StkUsed 0 R << idle >> 00000000 32.927724 308/512 1 HOOKS 00000000 0.034267 372/768 2 R CONSOLE 00000000 0.116763 468/768 3 HOSTCMD 00000000 0.000641 372/512 4 KEYPROTO 00000000 0.000042 212/512 5 KEYSCAN 00000000 0.000908 356/512 IRQ counts by type: 38 2932 155 1 158 261 160 67 Service calls: 87 Total exceptions: 3348 Task switches: 167 Task switching started: 0.001999 s Time in tasks: 33.282819 s Time in exceptions: 0.164717 s Change-Id: I234085cec231cd855d2a5e639ea1b0966c61d796 Reviewed-on: https://chromium-review.googlesource.com/296939 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: add peci control modulestabilize-7204.BDino Li2015-06-241-1/+2
| | | | | | | | | | | | | | | | | | | Add peci control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command "pecitemp" get CPU temperature normally. 2. console command "peci" manual test peci commands. (GetDIB, GetTemp, RdPkgConfig, and WrPkgConfig) Change-Id: I48b63a391adf04f159adca401acb369a6acc3799 Reviewed-on: https://chromium-review.googlesource.com/265171 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* ite: Add initial support for ITE IT8380 chipVincent Palatin2014-01-081-0/+87
Initial support for the ITE IT8380 chip with the following peripherals : - 8250-like UART module. - HW timer (with a 128-us tick period). - GPIO with pins initialization and edge interrupt support. other functions are stubbed. - Clock : basic fixed frequency setup only. It also add the dev board configuration as a test vehicle. Signed-off-by: Alec Berg <alecaberg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23575 TEST=make BOARD=it8380dev on IT8380 dev board, use the EC serial console, use gettime from console. Change-Id: Id4bf37d1beb21d1a4bee404c9a0bc500025fe787 Reviewed-on: https://chromium-review.googlesource.com/175481 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
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