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* stm32: assume no vbnvJack Rosenthal2021-02-033-34/+2
| | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_VBNV_CONTEXT is deprecated and removed. Cleanup preprocessor statements to assume it's never defined. This makes CONFIG_STM32_RESET_FLAGS_EXTENDED obsolete, since it's now always defined, so that gets removed too. BUG=b:178689388 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id040ce2ceca95ecde37de0014aafdbfd3087e00d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2668688 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* npcx: remove VBNVCNTXT storage in bbramJack Rosenthal2021-02-022-14/+5
| | | | | | | | | | | | | | Nothing uses this anymore, we can free up these indexes for future use. BUG=b:178689388 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id7df3091edc3a8d8d07ebdfb0347a26a51389163 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2668690 Reviewed-by: Edward Hill <ecgh@chromium.org>
* it83xx: deprecate BRAM_IDX_NVCONTEXTJack Rosenthal2021-02-022-13/+1
| | | | | | | | | | | | | | | Unused, as VBNV storage in EC bbram is gone. This makes inxedexs 0x10 to 0x1F in bbram available for future use. BUG=b:178689388 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I013bc2885f06aa853b1fbdabe98d9e5658811e44 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2668689 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Remove CONFIG_HOSTCMD_VBNV_CONTEXTJack Rosenthal2021-02-021-10/+0
| | | | | | | | | | | | | | This is no longer set by any boards, and we don't intend to use it on future projects again. BUG=b:178689388 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I7aa64d52bc197778873e7eb880961c37fb9f34e6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2657721 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* spi: Pass in spi_device as argument to spi_enable instead of portTom Hughes2021-01-2812-122/+85
| | | | | | | | | | | | | | | | | | | | | | Rather than passing in the port and iterating over the global spi_devices variable, pass in the specific spi_device that is being enabled/disabled. The spi_device_t struct has the port. This change makes the functions in spi.h more consistent since they now all take a spi_device_t*. This change is the first step in making the SPI configuration more dynamic. BRANCH=none BUG=b:177908650 TEST=git grep 'spi_enable(CONFIG' => no results TEST=make buildall TEST=Flash dragonclaw v0.2 and view console to verify FP sensor ID Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I64124e0ebcf898e88496acb77703b5f59ae931c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2654081 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* npcx7: Set the erase size to 64 KiBKeith Short2021-01-271-15/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NPCX flash layout was setting the erase size based on RO image size to ensure the host can erase the entire image using. When 1/2 flash is smaller than code RAM, the NPCX reserves one 4 KiB flash block for the NPCX header. This has the side effect of reducing the erase block size from 64 KiB to 4 KiB, and introduces a boot time regression when processing flash blocks. CL:2325764 modified the common flash support to allow the host to program up to CONFIG_WP_STORAGE_SIZE bytes for the RO image and CONFIG_EC_WRITABLE_STORAGE_SIZE bytes for the RW image. Set the erase size to a fixed value of 64 KiB, with build checks to verify the total flash size is a multiple of 64 KiB. Both the RO and RW image starting addresses are already aligned to at least a 64 KiB boundary, so there is no impact when the RW firmware is upgraded. BUG=b:175115527 BRANCH=volteer TEST=make buildall TEST=Boot EC on Delbin with NPCX797FC TEST=Increase the RW image size to 0x3ed1c (maximum is 0x3F000) and verify EC software sync is successful at updating the image. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I8823da2b909dfa36646b411a146001c618ce0e8c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2643579 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* npcx: fan: fix the enumeration of the tachometer clockWealian Liao2021-01-261-1/+1
| | | | | | | | | | | | | | | | | | NPCX chip uses MFT as a tachometer module. The counter clock select is not synced with the datasheet. For the LFCLK, the value of clock select should be set to 4. This CL fix the LFCLK clock enumeration. BUG=b:178376892 BRANCH=None TEST=pass buildall TEST=use PWM to generate the waveform to the tachometer. Check that the tachometer gets the correct value by 'faninfo'. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I22f47e0de403b144a8604e818db8f230764b4fc0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2649292 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* chip/npcx/pwm: update commentCaveh Jalali2021-01-201-1/+1
| | | | | | | | | | | | | | | This corrects a confusing comment on what pwm_set_duty(). BRANCH=none BUG=none TEST=none Change-Id: I6b3a094dafcbe10004ffbd76426e3398d8ef59de Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2639853 Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* shi: Fix TX buffer synchronization by leaving a gap on filling statusWai-Hong Tam2021-01-151-12/+18
| | | | | | | | | | | | | | | | | | | | | | | The original code fills out the entire TX buffer with status byte. AP keeps pulsing the clock and tries reading status. EC DAM may read the TX buffer during the write to response AP. A race may happen. Should leave a gap, like the gap for the PREAMABLE, when filling TX buffer. The critical section of filling the TX buffer should be done within the gap. It guarantees no race as DAM just reads the old status. It may result one- or two-byte extra status response. BRANCH=Trogdor BUG=b:177021164,b:168682309 TEST=Reflashing different firmware images to trigger TCPC update. No error happens for >20 rounds. Change-Id: I842d7011f85ef9323fba2af01b9062a5166d38f4 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628456 Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/gpg1 reset EC: handle case of watchdog resetstabilize-13729.16.B-mainDino Li2021-01-151-6/+24
| | | | | | | | | | | | | | | This CL triggers GPG1 HW reset after a EC watchdog. So the EC_RST_ODL signal will be toggled after the reset. BUG=b:173075595 BRANCH=none TEST=trigger watchdog to reboot system and verified system is able to boot to kernel. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I5d7a88dbb4bdb00977bc1fa02e5fa61e52347104 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627536 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-1532-58/+58
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* chip/mt8192_scp: add memory barrierTzung-Bi Shih2021-01-142-0/+2
| | | | | | | | | | | | | | | | | | | | | Writing to SCP SYS (e.g. SCP_GIPC_IN_CLR) is asynchronous and is slower than writing to CSR (e.g. CSR_VIC_MIEMS). There is a race condition if writing to MIEMS before acknowledging to interrupt sources. GVIC will re-latche interrupts wrongly. Adds memory barrier between them. The issue is exposed when enabling LTO because task_clear_pending_irq() will be inlined. BRANCH=none BUG=b:176959740 BUG=b:177289443 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I5cbf94d3db08c051f360e927b52514041dba769d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2624369 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* npcx/system: LCT compensate for MTC in PSL_hibernateWealian Liao2021-01-124-7/+69
| | | | | | | | | | | | | | | | | | | | | NPCX chip uses the MTC module as the RTC counter. However, in PSL hibernate, MTC will stop counting. NPCX9 supports the LCT module which could count continuously when VCC1 power is off. The CL uses LCT to compensate for the MTC counter value after PSL hibernate wake-up. The LCT maximum counting value is 16 weeks. BRANCH=none BUG=b:165777478, b:171919875 TEST=pass "make buildall" TEST=Check the RTC value in the following scenario: 1. "hibernate" and wake up EC by PSL input. 2. "hibernate 30" and wake up EC after timeout. 3. "hibernate 30" and wake up EC by PSL input before timeout. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I39e370a437f40749acbd3a35a8b37ebec70f1bf2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2506864 Reviewed-by: Keith Short <keithshort@chromium.org>
* chip: npcx: remove comment about keeping things in sync with zephyrJack Rosenthal2021-01-081-6/+1
| | | | | | | | | | | | | | | This is no longer needed as Zephyr does not rely on chip directory anymore. BUG=b:175249000 BRANCH=none TEST=none Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I6f42ba1a16be5e874530f42412b4bf9c2853ee65 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615131 Commit-Queue: Yuval Peress <peress@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org>
* ish: enable handling reset in AON codeLeifu Zhao2021-01-081-1/+8
| | | | | | | | | | | | | | | | | Enable handling reset in AON code for ish 5.4 on tgl rvp. BUG=b:176689775 BRANCH=none TEST=ish reset properly when host reboot. Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I9d53d668bf5b459e21519cab4fcaa28c753ff266 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607954 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* version: Rename version.h to cros_version.hYuval Peress2021-01-075-5/+5
| | | | | | | | | | | | | | | This change simply moves the include/version.h file over to avoid a naming collision with zephyr's version.h. BRANCH=none BUG=b:167392037 TEST=make buildall -j Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ib41b3c21817d5f81e713d3b550bc46a0d1c55cf8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612772 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* ish: enable GPIO wake from low power stateLeifu Zhao2021-01-072-0/+8
| | | | | | | | | | | | | | | | | Enable GPIO wake from low power state for ish 5.4 on tgl rvp. BUG=b:176670515 BRANCH=none TEST=Sensor GPIO interurpt can successfully wake up ish. Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: Id3eb997ad8dded95c154250e64cd3a5b287bb3d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607953 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Jett Rink <jettrink@chromium.org> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* it83xx/system: introduce GPG1 reset EC featureDino Li2021-01-071-0/+7
| | | | | | | | | | | | | | | | | This CL added option of CONFIG_IT83XX_HARD_RESET_BY_GPG1. If we enabled the option, EC will assert GPG1 pin to reset itself instead of triggering an internal reset while receiving a reset request. BUG=b:173075595 BRANCH=none TEST=Enable CONFIG_IT83XX_HARD_RESET_BY_GPG1 and check if GPG1 goes high while receiving reset command. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I930424c374dcbd742b8ecca7a1fa720699d42bb6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612233 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/spi: add support emmc boot modeDino Li2020-12-293-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | IT81202 bx version can configure SPI module to work as eMMC boot mode to catch CMD0. Once this mode is enabled, SPI's CS# pin isn't required. HW will drop data until CMD goes low (CMD0 starts with 01b) and saving 128 bytes in RX FIFO. FW need to parse the data of FIFO and handle argument of CMD0 (GO_IDLE_STATE, GO_PRE_IDLE_STATE, and BOOT_INITIATION). Pinmux of eMMC boot mode are as following: GPM2->CLK GPM3->CMD GPM6->DATA0 BUG=b:170795623 BRANCH=none TEST=boot to kernel on Juniper (replace EC with it81202 bx). Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I1dac1848bfd79f4a7dc02e1d90905e0cd6b8af3f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2604802 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* npcx9: remove unnecessary default CONFIGs for internal flashWealian Liao2020-12-281-2/+0
| | | | | | | | | | | | | | | | | | | | In npcx9, the internal flash is accessed via FIU/UMA (implementing in chip/npcx/flash.c). It won’t use the common/spi_flash.c to access the internal flash. This CL remove the two default configs related to the SPI flash in the npcx9 chip config and fix the npcx9_evb setting for the SPI flash. BRANCH=none BUG=b:165777478 TEST=buildall pass Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I7c525791d001fa2833b7d895f277768948783938 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600807 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* chip/stm32/usb_hid_keyboard: Implement HID GET_REPORTNicolas Boichat2020-12-231-3/+9
| | | | | | | | | | | | | | | Implement HID GET_REPORT with INPUT type. BRANCH=nocturne,kukui BUG=b:174539061 TEST=With associated kernel CL: cd /sys/bus/usb/drivers/usbhid echo 1-1.1:1.0 > unbind; echo 1-1.1:1.0 > bind Change-Id: If62c92e55fa5454116816681c2ab46d5e796c4b5 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2578620 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* tcpm: Move tcpm.h into an include directorySimon Glass2020-12-221-1/+1
| | | | | | | | | | | | | | | | | | This header file is used from quite a few files, relying on the EC build system to find includes in the driver/tcpm directory. For Zephyr we don't want to add that as an include. It makes more sense for header files to be in an include directory, so move it and fix up the users. BUG=b:175434113 BRANCH=none TEST=build Zephyr and ECOS on volteer Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I5851914b1a7d3fdc1ba911c0fbe9046afbaf6f5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597985 Reviewed-by: Keith Short <keithshort@chromium.org>
* stm32g4: ucpd: Add missing tcpci methodsScott Collyer2020-12-223-3/+103
| | | | | | | | | | | | | | | | | This CL adds a VCONN enabe/disable support function to remove the pull resistor and 2 addiltional functions which are required to complete the stm32gx tcpci driver. BUG=b:167601672 BRANCH=None TEST=verfied type-c attaches properly on quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I5a3732f15a5a0af9d372ae37475e9e8bdd3914b4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2588850 Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* stm32g4: ucpd: Add pd msg log and console debug commandsScott Collyer2020-12-221-3/+415
| | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds code to the ucpd driver which can used for additional debug information about both usbc and usb-pd information. The message log contains up to 64 entries which is sufficient to establish a connection and enter alt-dp mode. BUG=b:167601672 BRANCH=None TEST=Connect quiche on host port and validate debug commands: > ucpd info cc1 = Rp cc2 = Rp Rp = Rp_3.0 cc1_v = 1 cc2_v = 2 rx_en = 1 pol = 1 Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I2f50a6284336f21e833ecdff72746ff04c191b52 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2531183 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* Revert "npcx9: remove unnecessary default CONFIGs for internal flash"Hung-Te Lin2020-12-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit a3dd3c3a941794bd6efcdfac0b70bfae7441ed29. Reason for revert: chromium:1161113 board/npcx9_evb/board.c:103:4:error: CONFIG_SPI_FLASH_PORTundeclared here Original change's description: > npcx9: remove unnecessary default CONFIGs for internal flash > > In npcx9, the internal flash is accessed via FIU/UMA (implementing in > chip/npcx/flash.c). It won’t use the common/spi_flash.c to access the > internal flash. Let’s remove these two default CONFIGs to prevent > people from confusing. > > BRANCH=none > BUG=b:165777478 > TEST=buildall pass > > Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> > Signed-off-by: CHLin <CHLin56@nuvoton.com> > Change-Id: Id04dc9ff5402262b5cdf0815ae953ced777b5d96 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597124 > Reviewed-by: caveh jalali <caveh@chromium.org> Bug: chromium:1161113 Change-Id: I57fb92418e71f8ce0ffd77bad34d4e5055552af1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600713 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Auto-Submit: Hung-Te Lin <hungte@chromium.org>
* npcx9: remove unnecessary default CONFIGs for internal flashWealian Liao2020-12-221-2/+0
| | | | | | | | | | | | | | | | | In npcx9, the internal flash is accessed via FIU/UMA (implementing in chip/npcx/flash.c). It won’t use the common/spi_flash.c to access the internal flash. Let’s remove these two default CONFIGs to prevent people from confusing. BRANCH=none BUG=b:165777478 TEST=buildall pass Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: Id04dc9ff5402262b5cdf0815ae953ced777b5d96 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597124 Reviewed-by: caveh jalali <caveh@chromium.org>
* Cleanup: rename function nameRuibin Chang2020-12-211-2/+2
| | | | | | | | | | | | | | | | | Rename function name from it83xx_* to it8xxx2_* for it8xxx2 driver. Rename function name from *_tcpm_sw_reset to *_tcpm_hook_disconnect. BUG=none BRANCH=none TEST=make BOARD=drawcia -j make BOARD=asurada -j Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I8111ec5b9972d1badae625e87248c62e99eabbf6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2598298 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* it8xxx2: enable ILM0Dino Li2020-12-174-0/+45
| | | | | | | | | | | | | | | | | | This change enable ILM0 for it8xxx2 series, so we can pull more code into static cache to save latency of fetching code from flash. BUG=b:171172053 BRANCH=none TEST=Check timestamp of "Inits done" on asurada: Before the change was made, we got the timestamp is: [0.004408 Inits done] With this change, the timestamp is changed to: [0.003843 Inits done] Change-Id: Ie7a241bed2f926fd0034cecaf5d8e8183ca16d2e Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563056 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/flash: workaround of IMMU tag is nds32 onlyDino Li2020-12-171-4/+11
| | | | | | | | | | | | | | This change excluded the workaround from core riscv. BUG=b:111808417 BRANCH=none TEST=On asurada and drawcia, no error while erasing and writing flash of address 0x7e000 ~ 0x7f000 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: If6510b181173862684552607d688b3afb046aa2c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563356 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: Don't delay hibernate wake by 2 seconds (v2)Edward Hill2020-12-162-11/+12
| | | | | | | | | | | | | | | | | | | | | | | Revert CL:2576439 and try again, this time checking for EC_RESET_FLAG_HIBERNATE before setting EC_RESET_FLAG_INITIAL_PWR. The problem with the first attempt was on sysjump to RW after wake from hibernate. Then gpio_pre_init() saw EC_RESET_FLAG_INITIAL_PWR but not EC_RESET_FLAG_HIBERNATE and so added an unwanted 2 second delay because system_common_pre_init() hadn't yet restored the flags from before the jump. Moving the check for EC_RESET_FLAG_HIBERNATE into check_reset_cause() avoids this issue. BUG=b:173180800 BRANCH=zork TEST=no 2 second delay on wake from hibernate, for both RO boot and jump to RW. Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ia1bfba5740d77961ccc7e140da80be1070700b1e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2592501 Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* chip/mt8192_scp: add memory barrier after writing to cacheTzung-Bi Shih2020-12-161-2/+12
| | | | | | | | | | | | | | Writing to AXI is asynchronous. Adds memory barrier to writeback and flush cache operations to make sure the writing is done. BRANCH=none BUG=b:175512991 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I6d04a2604f4eddae54aee4ba3ee4600e909e2784 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2592299 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* chip/mt8192_scp: make all cache operations inlineTzung-Bi Shih2020-12-162-110/+97
| | | | | | | | | | | | | Makes all cache operations inline. BRANCH=none BUG=b:175512991 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I6d2e8752b4be63257854630a83c74aca21e0d799 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2592298 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* chip/mt8192_scp: set CONFIG_PROGRAM_MEMORY_BASE_LOADTzung-Bi Shih2020-12-161-0/+1
| | | | | | | | | | | | | | Sets CONFIG_PROGRAM_MEMORY_BASE_LOAD to separate VirtAddr and PhysAddr in the final ec.obj. BRANCH=none BUG=b:173753688 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: If839ffb5cc63c945492dbc20c12542a93b0ae569 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2553997 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* task_set_event: remove the wait argumentDawid Niedzwiecki2020-12-1420-39/+34
| | | | | | | | | | | | | | | | | | | | There is an option in the task_set_event function which force the calling task to wait for an event. However, the option is never used thus remove it. This also will help in the Zephyr migration process. BUG=b:172360521 BRANCH=none TEST=make buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* stm32g4: ucpd: Add support for USB-PD messagingScott Collyer2020-12-133-26/+729
| | | | | | | | | | | | | | | | | | | | | This CL adds routines required to support USB-PD messaging to the UCPD driver. UCPD is performs TCPC type functions, but is not a TCPC. UCPD does utilize the common TCPCI APIs as entry points called from the port's PD task. In addition, UCPD has its own task to manage more easily transmit requests from TCPM layer and GoodCRC messages which must be intiated in the UCPD driver itself. BUG=b:167601672 BRANCH=None TEST=verfied type-c attaches properly on quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I0c02bee4badc479125832a6b5a6fa156e998c201 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2247117 Tested-by: Scott Collyer <scollyer@chromium.org> Auto-Submit: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* COIL: Standardize i2c peripheral languageDossym Nurmukhanov2020-12-124-86/+85
| | | | | | | | | | | BUG=none TEST=validate volteer build (i2c_peripheral.c is not used by any boards) BRANCH=none Signed-off-by: dossym@chromium.org Change-Id: Ib2d78dc3fc9f4f189f84409cf43ab96788c429be Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2587227 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* COIL: Rename i2c_peripheral filesDossym Nurmukhanov2020-12-122-2/+2
| | | | | | | | | | | | BUG=none TEST=build and run on volteer BRANCH=none Signed-off-by: dossym@chromium.org Change-Id: I11a75e4954e918b2d4ff575dee14dec621a619b3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2587226 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chip/mt8192_scp: expose PMU-related functionsTzung-Bi Shih2020-12-101-0/+6
| | | | | | | | | | | | | | | Exposes PMU-related functions so that we can call the functions to study some part of cache performance. BRANCH=none BUG=b:172988651 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I27182e3d2af52d8761f45359f3627d70c5acf28c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567517 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* chip/mt8192_scp: invalidate all I/D cache when resetting PMUTzung-Bi Shih2020-12-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When resetting PMU, also: - invalidates I-cache - flushes D-cache > enable_pmu i select "I" > show_pmu cycles: 1228599543 retired instructions: 80706 I-cache: access: 55089 miss: 179 (0.32%) non-cacheable I: 0 > enable_pmu d select "D" > show_pmu cycles: 970961198 retired instructions: 32638 D-cache: access: 12598 miss: 80 (0.63%) non-cacheable D: 972 Expect to see the increasing "miss" counts. BRANCH=none BUG=b:172988651 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ib779bd224cd39ff8de05d1568028ef63b189ecb4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567516 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* npcx: Don't delay hibernate wake by 2 secondsEdward Hill2020-12-071-1/+5
| | | | | | | | | | | | | | | Waking from PSL hibernate is power-on for EC but not for H1, so we should not add the 2 second delay for CONFIG_BOARD_RESET_AFTER_POWER_ON in this case. BUG=b:173180800 BRANCH=zork TEST=no 2 second delay on wake from hibernate Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ib0c8f2ca7f197626b20a11e21ace44a5046db18b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2576439 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* stm32: low power configuration for STM32F4Vincent Palatin2020-12-021-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | As most of the peripherals were not implemented to support switching to 16-MHz HSI (e.g. high speed serial port requires a clock input > 24 Mhz), implement a simpler clock scheme than the dynamic between HSI and PLL used other platforms: - the PLL is disabled only when entering the low-power idle and the PLL locking time is added to wake-up time. - when the host is running (not suspended) we stay in a high power mode (~20mW). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=b:130561737 TEST=manual, on bloonchipper, check we can still capture fingerprint. read the MCU power consumption: pp3300_dx_mcu_mw is 2.367 mW. BRANCH=fpmcu-bloonchipper Change-Id: Ic1fe015b2501bdea9779a2f63fab296f8812c315 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2555162 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: add STOP mode on STM32F4Vincent Palatin2020-12-021-2/+117
| | | | | | | | | | | | | | | | | Implement a low power idle mode using the STM32F4 STOP mode. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=b:130561737 TEST=manual, on bloonchipper, check we can still capture fingerprint. read the MCU power consumption. BRANCH=fpmcu-bloonchipper Change-Id: I11249e9b68c989033263e34e1cde3f19ffe7c54c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2537631 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: fix RTC rounding error breaking alarmsVincent Palatin2020-12-021-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On STM32F4, when converting micro-seconds to the RTC sub-second counter value, the current computation in the us_to_rtcss() routine has a large rounding error which can even led to generate a negative value. When such a negative value is output and then programmed in the (unsigned) RTC_ALRMASSR register used to set the alarm precise sub-second timestamp, it might put a wrong value in the past. As a consequence when the RTC alarm is used a wake-up mechanism for the low power idle, it might never fired and trigger a watchdog reboot. An example of bad values on a STM32F412 with the RTC driven by the 32-kHz LSI: - RTC_PREDIV_A = 1 - RTC_FREQ = (STM32F4_LSI_CLOCK / (RTC_PREDIV_A + 1) = 16000 /* Hz */ - RTC_PREDIV_S = (RTC_FREQ - 1) = 15999 - US_PER_RTC_TICK = 1000000 / RTC_FREQ = 62 /* rounded from 62.5 */ When converting 996000 us, us_to_rtcss(996000) = RTC_PREDIV_S - (us / US_PER_RTC_TICK) = 15999 - (996000 / 62) = -65 returned as a uint32_t as 0xfffffffb. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=b:130561737 TEST=manual, with the STOP mode enabled, we no longer see watchdog reboot due to the RTC alarm being set in the past and never firing. TEST=manual, verify that the output of the 'gettime' console command is not drifting compared to the wall clock when the low power idle using the RTC time is used. BRANCH=fpmcu-bloonchipper Change-Id: I53869539828bed9a5900d29407b5feba140b8217 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563684 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: add dynamic clocking for STM32F4Vincent Palatin2020-12-022-92/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allow to transition between the PLL to run at full speed and the bare HSI (internal RC oscillator at 16Mhz) to save power. On HSI, as our sysclk frequency is low, we run all peripheral clocks undivided at the same frequency. Keep the configuration for other platforms running from the HSE (external crystal) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=b:130561737 TEST=manual, verify the timers are working by checking the output of the 'gettime' console command against the wall clock. TEST=manual, verify the UART console works as expected. TEST=measure MCU power on bloonchipper in various modes through the INA: PLL 19.20 mW HSI 4.73 mW STOP 2.10 mW BRANCH=fpmcu-bloonchipper Change-Id: I1185e04c9a7819fec05dd643b7026116b146f3b8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2527049 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: update the timer pre-scaler on STM32F4Vincent Palatin2020-12-021-2/+3
| | | | | | | | | | | | | | | | | | | | | Add support for changing for the timer source clock frequency on STM32F4 by re-computing the timer pre-scaler value in the HOOK_FREQ_CHANGE callback. Preparatory work to implement power management switching between PLL and HSI as sysclk. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=b:130561737 TEST=manual, verify the output of the 'gettime' console command against the wall clock. BRANCH=fpmcu-bloonchipper Change-Id: Ia7dc24d3b1dbff816b1cebbc87492e678b987dfd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2527048 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* chip/mt8192_scp: support PMU counterTzung-Bi Shih2020-11-272-0/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supports performance monitor unit counters. Introduces new console commands: - enable_pmu - disable_pmu - show_pmu > enable_pmu X Parameter 1 invalid Usage: enable_pmu [I | D | C] > enable_pmu i select "I" > show_pmu cycles: 842443131 retired instructions: 32855 I-cache: access: 22324 miss: 0 (0.0%) non-cacheable I: 0 > enable_pmu d select "D" > show_pmu cycles: 1137656582 retired instructions: 36619 D-cache: access: 13779 miss: 0 (0.0%) non-cacheable D: 1072 > enable_pmu c select "C" > show_pmu cycles: 2656349519 retired instructions: 74746 control transfer instruction: total: 20767 miss-predict: 13346 (64.26%) interrupts: 262 BRANCH=none BUG=b:172988651 TEST=define DEBUG && make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I461ae51b84badb25e9b50ef1af7e3a81139cea47 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2562910 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* usb_hid_keyboard: implement vivaldi top row featureTing Shen2020-11-271-22/+73
| | | | | | | | | | | | | | | | | | This CL implements a feature report defined in [1] that describes the keyboard's top row layout. [1] http://doc/1NTxSGv3WA2Vn4dlPLOcvKBvPytWOF0UAcIYQaFctTug BUG=b:171156337 TEST=Verify feature report content using test code in CL:2530156. BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I28a93f1b926d58602eb66d1b090e89384cb09f77 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2522641 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* it83xx/i2c: adjust Tlow and Thigh of 400kHz clockDino Li2020-11-251-2/+2
| | | | | | | | | | | | | | | | This CL increased clock's Tlow to 1.51 us (1.3 us minimum) and reduced Thigh to 1.087 us (0.6 us minimum). BUG=b:163384683 BRANCH=none TEST=i2c clock meet timing at 400kHz. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Id62b2370018ba2d41e0dbc715a4c40629260d66b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2557281 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Mike Goodey <mgoodey@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip/it83xx: move __RAM_CODE_SECTION_NAMETzung-Bi Shih2020-11-202-1/+2
| | | | | | | | | | | | | | | | Moves __RAM_CODE_SECTION_NAME from registers.h to config_chip.h. Or switch.S cannot see the macro. BRANCH=none BUG=none TEST=1. make BOARD=asurada 2. grep __switch_task build/asurada/RW/ec.RW.smap Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I1ef272c2e2181a88e4f53dc3024330a1a26c0688 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2549342 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Diana Z <dzigterman@chromium.org>
* npcx: avoid checking value of undefined symbolCaveh Jalali2020-11-192-0/+8
| | | | | | | | | | | | | | | This sets a default value of 0 for NPCX_UART_MODULE2 and NPCX9_PWM1_SEL so that board files don't need to set these. BRANCH=none BUG=b:173575131 TEST=buildall Change-Id: Ief84ed558bb5431f13fb01b963db3bd97fc8d659 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2546639 Reviewed-by: CH Lin <chlin56@nuvoton.corp-partner.google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
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