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path: root/core/riscv-rv32i/task.c
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* tasks: Only report stack overflow if task is enabledRob Barnes2023-05-151-3/+5
* tasks: Add task_enabled functionRob Barnes2023-04-241-0/+5
* tree: Replace "unsigned" with "unsigned int"Andrea Grandi2023-01-041-1/+1
* tree: Remove CONFIG_SOFTWARE_PANICTom Hughes2022-10-121-2/+0
* Update license boilerplate text in source code filesMike Frysinger2022-09-121-1/+1
* tree-wide: const-ify argv for console commandsCaveh Jalali2022-09-011-2/+2
* util: remove unused includesYuval Peress2022-08-051-0/+2
* core/riscv-rv32i/task.c: Format with clang-formatJack Rosenthal2022-07-011-59/+48
* task: change task_set_event return type to voidFabio Baltieri2022-06-021-3/+1
* atomic: fix printing atomic_t typeDawid Niedzwiecki2022-01-061-4/+4
* atomic: change atomic_t to longDawid Niedzwiecki2021-12-171-4/+4
* task: use atomic_t for some variablesDawid Niedzwiecki2021-12-071-3/+3
* task: change task events bitmask to atomic_tDawid Niedzwiecki2021-11-291-2/+2
* task: Use bool for truthy return typesTom Hughes2021-11-091-4/+4
* tree: Make all console commands staticTom Hughes2021-10-151-1/+1
* Provide 'is_interrupt_enabled' function for all coresPatryk Duda2021-09-061-0/+10
* riscv-rv32i/task: Remove the remove_me functionDino Li2021-04-081-12/+0
* core/riscv-rv32i: set in_interrupt at beginning of exception handlerTzung-Bi Shih2021-02-191-4/+1
* riscv-rv32i: store EC interrupt number in panic infoDino Li2021-02-041-19/+10
* core/riscv-rv32i: correct inline assembly constraint modifierTzung-Bi Shih2021-01-141-1/+1
* task_set_event: remove the wait argumentDawid Niedzwiecki2020-12-141-6/+15
* atomic: rename atomic_read_clear to atomic_clearDawid Niedzwiecki2020-11-021-1/+1
* tree: Use new atomic_* implementationDawid Niedzwiecki2020-10-271-11/+10
* core: rename atomic_clear to atomic_clear_bitsDawid Niedzwiecki2020-10-061-4/+4
* tree: rename atomic_* functions to deprecated_atomic_*Jack Rosenthal2020-09-291-10/+11
* it83xx: read_clear_int_mask() read and clear interrupt bit.Dino Li2020-09-241-8/+8
* core: nds32/riscv-rv32i: fix issue of time in exceptions is negativeDino Li2020-07-241-7/+8
* ec: change usage of "sane" per inclusive languagePaul Fagerburg2020-07-221-1/+1
* riscv-rv32i: correct printf formatEric Yilun Lin2020-07-221-7/+7
* core/riscv-rv32i: set volatile for in_interruptTzung-Bi Shih2020-06-101-1/+1
* core/riscv-rv32i: add error handling for chip_get_ec_int()Tzung-Bi Shih2020-06-041-1/+10
* core/riscv-rv32i: add in_soft_interrupt_context()Tzung-Bi Shih2020-06-031-0/+6
* core/riscv-rv32i: remove get_sw_int()Tzung-Bi Shih2020-05-291-9/+1
* core/riscv-rv32i: add default __idle()Tzung-Bi Shih2020-05-191-0/+4
* core/riscv-rv32i: clean up header inclusionsTzung-Bi Shih2020-05-191-4/+4
* core/riscv-rv32i: do not expose get_sw_int()Tzung-Bi Shih2020-05-191-1/+1
* core/riscv-rv32i: move interrupt details to IT83XX specificTzung-Bi Shih2020-05-191-9/+2
* Remove uses of %lEvan Green2019-10-051-4/+4
* core/riscv-rv32i: misc fixesDino Li2019-10-021-30/+26
* task: Add task_enable_task() and task_disable_task()Yilun Lin2019-08-221-0/+13
* core:RISC-V / chip:IT83202Dino Li2019-06-111-0/+716
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