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* core/riscv-rv32i: set volatile for in_interruptTzung-Bi Shih2020-06-101-1/+1
* hooks: Introduce HOOK_CHIPSET_SHUTDOWN_COMPLETEWai-Hong Tam2020-06-066-0/+24
* core/riscv-rv32i: remove return valuesTzung-Bi Shih2020-06-042-12/+6
* core/riscv-rv32i: add error handling for chip_get_ec_int()Tzung-Bi Shih2020-06-042-10/+21
* core/riscv-rv32i: add in_soft_interrupt_context()Tzung-Bi Shih2020-06-031-0/+6
* test: Pass commandline arguments to run_testTom Hughes2020-05-301-1/+1
* test: Add on-device test for calculating MPU regions for RWYicheng Li2020-05-303-18/+36
* cortex-m: Use MPU REGION_CODE_RAM to lock rollback if neededYicheng Li2020-05-291-1/+1
* cortex-m: Lock RW flash using aligned MPU regionsYicheng Li2020-05-291-5/+27
* core/riscv-rv32i: remove get_sw_int()Tzung-Bi Shih2020-05-292-18/+2
* cortex-m: Init the MPU to check for correct operationAndrew McRae2020-05-272-2/+25
* test: Add on-device MPU unit testTom Hughes2020-05-221-0/+3
* core/cortex-m: create private MPU header for use by unit testsTom Hughes2020-05-222-5/+29
* cortex-m/mpu: Check alignment when applying MPU configTom Hughes2020-05-221-10/+26
* cortex-m: Always enable MPU in mpu_pre_initTom Hughes2020-05-221-2/+5
* cortex-m: Configure rollback MPU based on number of regionsTom Hughes2020-05-221-4/+51
* cortex-m: Clean up MPU logicTom Hughes2020-05-222-18/+63
* core/riscv-rv32i: define dummy implementation for CPU_INTTzung-Bi Shih2020-05-191-0/+5
* core/riscv-rv32i: add default __idle()Tzung-Bi Shih2020-05-191-0/+4
* core/riscv-rv32i: clean up header inclusionsTzung-Bi Shih2020-05-193-10/+4
* core/riscv-rv32i: do not expose get_sw_int()Tzung-Bi Shih2020-05-194-12/+2
* core/riscv-rv32i: move interrupt details to IT83XX specificTzung-Bi Shih2020-05-194-40/+26
* core/riscv-rv32i: guard more IT83XX chip specific itemsTzung-Bi Shih2020-05-191-10/+7
* core/riscv-rv32i: separate CHIP_FAMILY_IT8XXX2 specific memory regionsTzung-Bi Shih2020-05-191-9/+55
* cortex-m: provide a function to set IRQ priorityPeter Marheine2020-05-194-18/+32
* ish: enable IPAPG for ish 5.4 on tgl rvp platformLeifu Zhao2020-05-151-0/+7
* risc-v: add comments about not needing 16-byte stack frame alignmentDino Li2020-05-133-7/+48
* core/cortex-m[0]: Move core functions assembly files to third_partyNicolas Boichat2020-03-256-765/+6
* core/cortex-m0/curve25519: Move code to third_party folderNicolas Boichat2020-03-257-3240/+1
* chip/it8xxx2: add support IT81302 and IT81202Dino Li2020-03-211-0/+15
* Rename Cortex-M MMFS to CFSRPeter Marheine2020-03-192-50/+34
* remove cr50 related filesNamyoon Woo2020-03-091-6/+0
* ish: infrastructure changes to support ish5.4 PMLeifu Zhao2020-02-271-1/+3
* core/riscv-rv32: link libgcc for 64-bit divisionDino Li2020-02-251-0/+1
* host: Add basic taskinfo console commandCraig Hesling2020-02-051-0/+22
* riscv-rv32i: Add sqrtf functionDino Li2020-01-223-1/+33
* core/riscv-rv32i: enable software ctzDino Li2020-01-221-0/+5
* core/system: Extract and doc cortex constCraig Hesling2020-01-132-1/+12
* core/riscv-rv32i: Format linker scriptCraig Hesling2019-12-161-221/+228
* core/nds32: Format linker scriptCraig Hesling2019-12-161-213/+217
* core/minute-ia: Format linker scriptCraig Hesling2019-12-161-10/+10
* core/host: Format linker scriptCraig Hesling2019-12-161-117/+117
* cortex-m/m0: Reformat linkers script with tabsCraig Hesling2019-11-262-604/+635
* core/nds32 and riscv-rv32i/ec.lds.S: no assert if section is not presenttim2019-11-222-2/+4
* ish: chip enablement of ish5.4 on tgl rvp platformLeifu Zhao2019-11-091-1/+3
* host: remove leftovers from using system clock in testsJack Rosenthal2019-10-251-21/+0
* test: don't rely on system time for testsJett Rink2019-10-141-6/+10
* usbc: fix flaky testsJett Rink2019-10-101-0/+5
* Remove uses of %lEvan Green2019-10-052-7/+4
* printf: Fix formatting errorsEvan Green2019-10-051-1/+1
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