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* Update license boilerplate text in source code filesMike Frysinger2022-09-121-1/+1
| | | | | | | | | | | | | | | Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* pd: Remove ACCESSORY statesShawn Nematbakhsh2017-10-191-28/+0
| | | | | | | | | | | | | | | | | | | According to the USB-C spec, when a debug accessory is identified, we may optionally establish USB PD communication over CC. Some DTS partners (eg. servo_v4) expect us to speak PD, so let's make it so. There is no need for special ACCESSORY states, these do not exist in the PD spec. BRANCH=servo BUG=chromium:737755,b:65837068 TEST=On scarlet, attach servo_v4 and verify scarlet charges. Also verify EC and cr50 consoles are available through servo_v4. Change-Id: I59d1ca50b4766509eccf38562cdf926578138585 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/693294 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: pd: Remove CONFIG_CASE_CLOSED_DEBUGShawn Nematbakhsh2017-10-051-8/+0
| | | | | | | | | | | | | | | | | | CONFIG_CASE_CLOSED_DEBUG (CCD functionality implemented by EC) is no longer used in conjunction with CONFIG_USB_POWER_DELIVERY, and the common routines are only used by one board. BUG=chromium:737755 BRANCH=None TEST=`make buildall -j` Change-Id: Idc3d2fccef6cbec2af786cef634d752a02a0e859 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/656315 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: Defragment codeRandall Spangler2017-09-091-152/+0
| | | | | | | | | | | | | | | | | For historical reasons, CCD, reset, and power button control were scattered around several files. Consolidate the code in more sensible (in retrospect) places. No functional changes, just moving code. BUG=none BRANCH=cr50 TEST=make buildall; boot cr50 Change-Id: Ic381a5a5d0627753cc771189aa377e88b81b155e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/653766 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Consolidate CCD device enableRandall Spangler2017-09-061-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the Cr50 state machines (EC, AP, RDD, bitbang, etc.) manage their own enabling and disabling of the ports (UART, SPI, etc.) This is tricky because the rules for when ports should be enabled are non-trivial and must be applied in the correct order. In additionl the changes all need to be serialized, so that the hardware ends up in the correct state even if multiple state machines are changing simultaneously. Consolidate all of that into chip/g/rdd.c. The debug command for it is now 'ccdstate', which just prints the state machines. This will allow subsequent renaming of the 'ccdopen', etc. commands to 'ccd open', etc. Also include UART bit-banging into that state which must be consistent. Previously, it was possible for bit-banging to leave UART TX connected, instead of returning it to the previous state. Use better names for CCD config fields for UART. I'd had them backwards. BUG=b:62537474 BRANCH=cr50 TEST=manual, with a CR50_DEV=1 image 1) No servo or CCD Pull SERVO_DETECT low (disconnected) Pull CCD_MODE_L high (disabled) Pull EC_DETECT and AP_DETECT high (on) Reboot. RX is enabled even if cables are disconnected so we buffer. ccdstate -> UARTAP UARTEC Pull EC_DETECT low. ccdstate -> UARTAP Pull EC_DETECT high and AP_DETECT low. ccdstate -> UARTEC Pull AP_DETECT high. ccdstate -> UARTAP UARTEC 2) Servo only still allows UART RX Pull SERVO_DETECT high (connected). ccdstate -> UARTAP UARTEC 3) Both servo and CCD prioritizes servo. Pull CCD_MODE_L low (enabled). ccdstate -> UARTAP UARTEC Reboot, to make sure servo wins at boot time. ccdstate -> UARTAP UARTEC Bit-banging doesn't work when servo is connected. bitbang 2 9600 even -> superseded by servo bitbang -> disabled ccdstate -> UARTAP UARTEC 4) CCD only allows more ports and remembers we wanted to bit-bang Pull SERVO_DETECT low. ccdstate --> UARTAP+TX UARTEC+BB I2C SPI bitbang 2 disable ccdstate --> UARTAP+TX UARTEC+TX I2C SPI Reboot and see we don't take over servo ports until we're sure servo isn't present. ccdstate --> UARTAP UARTEC (for first second) ccdstate --> UARTAP+TX UARTEC+TX I2C SPI (after that) 5) Bit-banging takes over ECTX bitbang 2 9600 even bitbang -> baud rate 9600, parity even ccdstate -> UARTAP+TX UARTEC+BB I2C SPI bitbang 2 disable ccdstate -> UARTAP+TX UARTEC+TX I2C SPI 6) Permissions work. Allow easy access to full console and ccdopen: ccdset OpenNoTPMWipe always ccdset OpenNoLongPP always ccdset GscFullConsole always Default when locked is full AP UART EC RO, no I2C or SPI ccdlock ccdstate -> UARTAP+TX UARTEC No EC transmit permission means no bit-banging bitbang 2 9600 even bitbang -> disabled ccdstate -> UARTAP+TX UARTEC But it remembers that we wanted to ccdopen ccdstate -> UARTAP+TX UARTEC+BB I2C SPI bitbang 2 disable ccdstate -> UARTAP+TX UARTEC+TX I2C SPI Try turning on/off permissions ccdset UartGscTxECRx always ccdlock ccdstate -> UARTAP+TX UARTEC+TX No read means no write either ccdset UartGscRxECTx ifopened ccdlock ccdstate -> UARTAP+TX ccdopen ccdset UartGscRXAPTx ifopened ccdlock ccdstate -> (nothing) Check AP transmit permissions too ccdopen ccdset UartGscRxAPTx always ccdset UartGscTxAPRx ifopened ccdlock ccdstate -> UARTAP Check I2C ccdopen ccdset I2C always ccdlock ccdstate -> UARTAP I2C SPI port is enabled if either EC or AP flash is allowed ccdopen ccdset flashap always ccdlock ccdstate -> UARTAP I2C SPI ccdopen ccdset flashec always ccdset flashap ifopened ccdlock ccdstate -> UARTAP I2C SPI Back to defaults ccdoops Change-Id: I641f7ab2354570812e3fb37b470de32e5bd10db7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/615928 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chip/g: use ccd_ext_is_enabled() instead of ccd_get_mode()Randall Spangler2017-09-011-0/+5
| | | | | | | | | | | | | | | | | | | Currently, only usb_pd_protocol.c cares about the actual ccd mode (disabled/partial/enabled). Everything else just cares whether it's enabled or not. So promote the boolean ccd_is_connected() from board/cr50 up to chip/g, and rename it to ccd_ext_is_enabled() to match the new nomenclature (since 'CCD' itself is now too overloaded). This will make it easier to handle CCD state directly in board/cr50 after we split it from common/case_closed_debug.c BUG=none BRANCH=cr50 TEST=make buildall; boot cr50; make sure USB endpoints still work Change-Id: Ic3df7467bfe29f1c5d7060cac1309a1f0e090d9e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648212 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: CCD V1 controls UART accessRandall Spangler2017-08-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AP and EC UART now use the CCD V1 capabilities to determine when access is allowed. Transmit to AP and EC can be toggled independently from read access to output from those UARTs. Note that disabling read access disables both transmit and receive. That is, it's not possible to set a UART where transmit is allowed but receive isn't. Why would you want to do that, anyway? See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 ccdoops ccdset cr50fullconsole always -> so we can use ccd command for testing ccd -> AP RX+TX, EC RX+TX ccdset uartecrx unlesslocked ccdset uartectx ifopened ccdset uartaprx always ccdset uartaptx unlesslocked ccdunlock ccd -> AP RX+TX, EC RX ccdlock ccd -> AP RX, EC disabled ccdoops ccdset cr50fullconsole always ccd -> AP RX+TX, EC RX+TX ccdset uartaprx ifopened ccdlock ccd -> AP disabled, EC RX Change-Id: I55db5897bb52cd60658ab221eadf5c59fc86744a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/595196 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_i2c: Fail if board I2C bridge is disabledRandall Spangler2017-07-311-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add usb_i2c_board_is_enabled(). On Cr50, this is now also connected to the I2C CCD capability. The USB-I2C bridge can only be used when the capability is available. On other platforms (Servo V4, etc.) where usb_i2c_board_enable() is a no-op, add a dummy implementation which always returns true. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 Connect host PC to dev board USB port On host PC: sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml dut-control pp3300_ec_shv_reg --> fail, error 0x8001 ccdoops --> reset I2C config ccd i2c disable --> I2C disabled On host PC: sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml dut-control pp3300_ec_shv_reg --> fail, error 0x0006 ccd i2c enable --> I2C enabled ccdunlock --> I2C disabled ccdoops --> I2C enabled ccdset i2c unlesslocked ccdlock --> I2C disabled ccdunlock --> I2C enabled Change-Id: Ia3df32e239a5f7c5915bc6c7e408ce0dc8b26c89 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/590577 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Disable CCD on board ID mismatchRandall Spangler2017-07-271-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If there is a board ID mismatch and rollback is not possible Cr50 firmware will enter a limited mode which only support Cr50 firmware upgrade. All other features must be disabled, because it is not possible to know which features should be allowed on the mismatched board. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 build, define CONFIG_CMD_CCDDISABLE ccdinfo --> state=opened ccddisable --> state=locked(disabled), all capabilities disabled ccdunlock --> access denied ccdopen --> access denied ccdreset --> access denied ccdpassword --> access denied ccdset --> access denied ccdoops ccdinfo --> state=opened, back to defaults Change-Id: Idb66fb1f3d5106aa0c2cb6addf2404ea9942b0d6 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/590070 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Preserve CCD state across deep sleepRandall Spangler2017-07-271-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define two bits in a long-life register to hold the current CCD state across deep sleep. Update the bits on CCD config change, and restore them on init. This is necessary because Cr50 loses RAM contents on deep sleep. It would be really inconvenient to open CCD, get a cup of coffee, and come back to find CCD has locked again because Cr50 was idle too long. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 build ccdinfo --> state=opened idle d ccdunlock ccdinfo --> state=unlocked (wait for deep sleep) sysinfo --> reset flags = hibernate wake-pin ccdinfo --> state=unlocked reboot sysinfo --> reset flags = hard ccdinfo --> state=opened Change-Id: I7864f374af5c159bc9691b094958fb030f3cb8ad Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/575996 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Add case closed debugging V1 configurationRandall Spangler2017-07-201-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the CCD configuration module, and the console commands to control it. It is not wired up to any of the CCD capabilities; that's coming in the next CL. Briefly: * CCD configuration is persistently stored in nvmem_vars. Use ccdinfo to print it. * CCD can be Locked, Unlocked (some capabilities), or Opened (all capabilities), using the ccdlock / ccdunlock / ccdopen commands. * CCD config can be restricted by setting a password via ccdpass. * Individual config capabilities can be set via ccdset. Some of those will be used to gate access to things like write protect and UARTs. Others affect the requirements for ccdunlock / ccdopen (for example, is physical presenc required). * The entire config can be reset via ccdreset. If only unlocked, config that is restricted to Opened is not reset. * If CR50_DEV=1, ccdoops will force-reset and open the config. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=none TEST=manual with CR50_DEV=1 build gpioget # make sure GPIO_BATT_PRES_L=0 ccdlock # lock, because CR50_DEV=1 builds start unlocked ccdinfo # locked, flags=0, all capabilities default ccdpass # access denied (we're locked) ccdreset # access denied ccdset flashap always # access denied ccdunlock ccdinfo # unlocked ccdpass foo ccdinfo # flags=2 (password set when unlocked) ccdset flashap always # access denied ccdset uartectx unlesslocked ccdinfo # yes, uartectx permission changed ccdlock ccdunlock # fails without password ccdunlock bar # wrong password ccdunlock foo # busy (wait 3 sec) ccdunlock foo ccdreset ccdinfo # no password, flags 0, capabilities all default ccdopen # requires physical presence; tap power or use 'pp' ccdset uartectx unlesslocked ccdset batterybypasspp ifopened ccdpass baz ccdinfo # password set, flag 0, ccdset changes worked ccdunlock ccdreset ccdinfo # uartectx back to ifopened, password still set ccdopen baz # still requires physical presence ccdset opennolongpp always ccdlock ccdopen baz # no pp required ccdset unlocknoshortpp unlesslocked ccdlock ccdopen baz # short pp sequence required (3 taps) ccdlock ccdunlock baz # short pp sequence required ccdopen baz # pp not required ccdset unlocknoshortpp always ccdlock testlab open # access denied testlab enable # access denied ccdunlock baz testlab open # access denied testlab enable # access denied ccdopen baz testlab enable # requires short pp ccdinfo # flags 1 ccdreset ccdinfo # no password, flags=1, caps all default ccdlock testlab open ccdinfo # opened testlab disable # requires short pp; let it time out ccdinfo # still opened, flags=1 ccdlock ccdoops # backdoor in CR50_DEV images to force-reset CCD ccdinfo # opened, flags=0, all defaults (yes, oops wipes out testlab) ccdreset rma ccdinfo # flags = 0x400000, everything but Cr50FullConsole always ccdreset # back to flags=0, all default Change-Id: I24e8d8f361874671e6e94f27492ae00db919bea9 Reviewed-on: https://chromium-review.googlesource.com/569439 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: use devid 0 and 1 to create a serial numberMary Ruthven2016-10-111-0/+5
| | | | | | | | | | | | | | | | | To be able to identify different cr50 devices connected to the same machine we need a serial number. This change uses dev id 0 and 1 to come up with one. BUG=chrome-os-partner:56641 BUG=chrome-os-partner:58342 BRANCH=none TEST=lsusb -vd 18d1:5014 | grep iSerial shows different numbers for different devices. Verify when ccd is disabled the serial number is 0. Change-Id: I85c54af4a21bdfd0542019c02aa8420d9a879fae Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/395633 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: connect to AP phy on reef when not in ccdMary Ruthven2016-08-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cr50 needs to connect to the AP phy when not in ccd so cr50 can be updated and used as a gnubby. This change uses the strapping options to detect when it is on reef and modifies the ccd behavior to initialize usb on the AP phy when ccd is disabled. On gru the cr50 behavior is unchanged. In RDD this change removes the checks that the current_map is the correct one based on the detected debug state. rdd_init calls rdd_interrupt to set up the usb and ccd state correctly. Having that check prevents that initial rdd_interrupt from calling rdd_detached. Before rdd_detached just disabled usb and we knew during init it would already be disabled. Now we want to make sure it is called if a debug accessory is not attached to initialize usb on the AP PHY. BUG=chrome-os-partner:56098 BRANCH=none TEST=manual verify ccd still works on gru disconnect suzyq and reset reef. run lsusb on the AP and verify it shows cr50 as a device. connect suzyq and check that the AP no longer sees cr50. disconnect suzyq and verify the AP sees it again Change-Id: I3c1ccc54895835bce12302f3ea43fc2e751b4c97 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/372920 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cleanup: fix all the header guardsBill Richardson2015-06-181-3/+3
| | | | | | | | | | | | | | | This unifies all the EC header files to use __CROS_EC_FILENAME_H as the include guard. Well, except for test/ util/ and extra/ which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively. BUG=chromium:496895 BRANCH=none TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029 Reviewed-on: https://chromium-review.googlesource.com/278121 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CCD: Remove CCD specific board connect and disconnectAnton Staaf2015-02-101-13/+0
| | | | | | | | | | | | | | | | | | | | Previously the Case Closed Debugging system provided a way for the board to connect and disconnect the CCD USB lines correctly, but this functionality is better implemented by board_set_usb_mux. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I697ee9740c64ac93557d9fca8b2d10e858c51193 Reviewed-on: https://chromium-review.googlesource.com/247721 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* ryu: Add minimal Case Closed Debug supportAnton Staaf2014-11-131-0/+49
This provides a framework for additional work. It exposes an API (ccd_set_mode) that can be used by the PD code to enable Case Closed Debug. Enabling CCD will result in the USB 2.0 lines on Ryu (proto 2) to be disconnected from the AP and for the USB peripheral to be enabled and connected to the host. The result is an enumerated device with no interfaces. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Enable CCD ryu_p2 and verify that it is enumerated by the host correctly. This requires a reworked Ryu (proto 2 with pullup). Change-Id: I1fbecdd5f94a61519cfc18c5e087892c6bd77fde Reviewed-on: https://chromium-review.googlesource.com/229139 Reviewed-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
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