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* power/mt8186: move ap-idle to highest priority at power_chipset_initTing Shen2023-05-171-8/+11
| | | | | | | | | | | | | | | | | | | AP_IDLE should have higher priority over AP_OFF. (note that in this version there's another bug that the S5->S0 hooks are not invoked when sysjump to RW) BUG=b:280408533 TEST=AP can boot to S0 after following steps: 1) dut-control power_state:rec 2) wait a few seconds to enter recovery screen 3) dut-control power_state:warm_reset Change-Id: I0b69f082f09afac93275bef7d93ca7123ab1099f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4387555 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Sung-Chi Li <lschyi@chromium.org>
* mt8186,mt8188: check the holder of AP_RST_ODLEric Yilun Lin2023-04-071-5/+29
| | | | | | | | | | | | | | | | | | | | | | | | | To distinguish the AP shutdown, and the AP reset held by GSC/Servo, we use the SYS_RST_ODL as the reference. If AP_EC_SYSRST_ODL is asserted, but SYS_RST_ODL is not, this is a normal shutdown. If AP_EC_SYSRST_ODL is asserted, and so is SYS_RST_ODL, the AP reset is held by GSC or Servo. In this case, we should let the power state stay at S0 to prevent from an unexpected shutdown. BUG=b:276229973 TEST=pass firmware_CorruptMinios TEST=dut-control warm_reset:on sleep:1 warm:reset:off, it stays at S0 BRANCH=none Change-Id: I9b69caa0d15e6e58e7f11ad1079536bc1954b5ce Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4402421 Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* mt8186,mt8188: fix chipset_force_shutdown before power_chipset_initEric Yilun Lin2023-04-061-1/+9
| | | | | | | | | | | | | | | | | | The power state is not reflect the actual power state before the power_chipset_init. When a chipset_force_shutdown is called before the task inited, the power state API will not reflect the actual state. This CL fix that by querying the signal state instead. BUG=b:276229973 TEST=pass firmware_CorruptMinios.minios_b BRANCH=none Change-Id: I0e48d9745039c6de460fd5579486fe5f3e74cda8 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4387196 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* mt8186: fix sysjump and hibernate actionsEric Yilun Lin2023-03-201-9/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. fix sysjump will boot the system with AP IDLE 1. fix boot with AP OFF 2. fix boot from hibernate The recent change which make the system staying at S5 for 10 seconds when AP power off. When sysjump requested, the RW part will automatically boot the system from S5 due to the initial in_exiting_off flag defaults to true. Since the exiting_off status is controlled by the power_chipset_init, we don't need the flag defaults to true on boot. Also, change the initial power state S5 to G3. They are the same in rail-wise on mt8186, but not in mt8188. Assign it as G3 to match mt8188 initial GPIO and rail states. When the AC on under hiberante, or the EC boots with AP OFF flag, this ensures the system stay at G3. BUG=b:274051287 b:274063396 b:274368558 TEST=pass firmware_ECPowerButton TEST=pass firmware_ECWakeFromULP TEST=dut-control cold_reset:on sleep:1 cold_reset:off, boot to S0 TEST=dut-control power_state:rec; dut-control power_key:tab. stay at S5->G3 TEST=hibernate, and AC on. The EC stays at G3. BRANCH=none Change-Id: I253f4956665a6a0edc2fe59c5a8a90a7c07a6180 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4349381 Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* mt8186,mt8188: skip forcing shutdown if AP is offEric Yilun Lin2023-03-151-1/+12
| | | | | | | | | | | | | | | | | | If the AP is off, we should stop calling chipset_force_shutdown() from re-doing shutdown. BUG=b:273657181 TEST=In S0, dut-control power_key:8.2, the chipset_force_shutdown is not called BRANCH=none Change-Id: I4413f984465f10d0f4b588cd6d80ead8464778bc Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4338759 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com> Auto-Submit: Eric Yilun Lin <yllin@google.com>
* mt8186,mt8188: fix warm reset issued by servo and gscEric Yilun Lin2023-03-151-9/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the EC holding SYS_RST_ODL (AP reset) in S3S5. Only asserting the SYS_RST_ODL with forcing shutdown. This will allow the AP to boot when the servo or gsc releases SYS_RST_ODL. When the AP is in reset, the power_state will be set to S5 first, and the target should be G3 if the power state has been put to G3 by S5 inactive timer. This is to prevent EN_PP4200_S5 and PMIC from being turned off, which would prevent the AP from booting when SYS_RST_ODL released if the AP reset was held by gsc or servo. To make it clearer, only three cases that we need to consider: 1. SYS_RST_ODL is held by GSC or Servo 2. SYS_RST_ODL is asserted by AP itself, a gracefully shutdown 3. SYS_RST_ODL is asserted by EC. For case 1, and 2, we don't need to assert SYS_RST_ODL, since the EC is not the initiator. BUG=b:267268982 b:273657518 TEST=On Steelix, and Geralt: * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control dut-control power_key:8.2 Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control dut-control power_key:9.2 Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control dut-control power_key:tab Result: G3 -> S0 * Console command: apreset Result: S0 -> S0, AP reboots * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 * AP console: reboot Reulst: S0 -> S0 * AP console: poweroff Reulst: S0 -> G3 * Short power press to power-on: $ dut-control dut-control power_key:tab Result: G3 -> S0 * Servo issue warm reset: $ dut-control power_state:warm_reset Result: S0 -> S5 -> S0 * Servo hold warm_reset and release: $ dut-control warm_reset:on sleep:2 warm_reset:off Result: S0 -> S5 -> S0 BRANCH=none Change-Id: I81fc25a5088722487fbbf74d641a5edf4ad450e5 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4338758 Tested-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Eric Yilun Lin <yllin@google.com>
* mt8188: add power signal PMIC_EC_RESETBEric Yilun Lin2023-03-101-0/+9
| | | | | | | | | | | | | | | | | | | | Add PMIC_EC_RESETB signal, which is used by PMIC to reset the AP. After the PMIC hard off triggered, we should wait for the PMIC reset the AP then we can safely remove the PMIC rail EN_PP4200_S5. BUG=b:267268982 TEST=scope the power signals changing is expected when 1. PMIC hard off 2. powerkey forcing shutdown 3. AP issue poweroff BRANCH=none Change-Id: I945d9f4ebbf6d53288c6503df7254ce448073565 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4290680 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* mt8188: fix PP4200_S5 enable/disable timingEric Yilun Lin2023-03-101-11/+10
| | | | | | | | | | | | | | | | The timing on/off timing should be moved to G3S5 and S5G3 to align the S5 naming. BUG=b:267268982 TEST=ensure the PG_PP4200_S5 is on/off at S5 state BRANCH=none Change-Id: I2ad6631125216a1400d169064389de38b1e1a60b Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4271050 Commit-Queue: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Eric Yilun Lin <yllin@google.com>
* mt8186,mt8188: fix power signal maskEric Yilun Lin2023-03-101-0/+1
| | | | | | | | | | | | | | | | The power_signal APIs need a POWER_SIGNAL_MASK shift before used. BUG=b:267268982 TEST=zmake BRANCH=none Change-Id: Id3e588756d309f872e86d60baba8ad82e0e87720 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4290679 Auto-Submit: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Eric Yilun Lin <yllin@google.com>
* mt8186,mt8188: increase PMIC hard off delay by 20% toleranceEric Yilun Lin2023-03-071-1/+2
| | | | | | | | | | | | | | | | | The PMIC hard off delay has a 20% tolerance, so increase the PMIC_HARD_OFF_DELAY to match the spec. BUG=b:267268982 TEST=zmake BRANCH=none LOW_COVERAGE_REASON=geralt bringup Change-Id: I822e6de7c75e9806763e3139f135e8f65c0bf171 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4290678 Tested-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* mt8186,mt8188: force turning off PMIC at S3S5Eric Yilun Lin2023-02-221-84/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL ensures that before going to S5, the PMIC has turned off the power source to AP, and we can move SHUTDOWN_COMPLETE to S3S5. It did this by asserting EC_PMIC_EN_ODL at S3S5. For pressing button shutdown, the flow becomes: S0 -> hold powerkey 8 seconds -> S3 -> S3S5 -> hold EC_PMIC_EN_ODL for 8 seconds -> S5 -> G3 For the other shutdowns: S0 -> S3S5 -> hold EC_PMIC_EN_ODL for 8 seconds -> S5 -> G3 Also, the AP won't boot when it's turning off the PMIC (S3S5) until it goes to S5. BUG=b:242012415 b:267268982 TEST=On Steelix, Tentacruel and Geralt: * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control dut-control power_key:8.2 Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control dut-control power_key:9.2 Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control dut-control power_key:tab Result: G3 -> S0 * Console command: apreset Result: S0 -> S0, AP reboots * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 * AP console: reboots Reulst: S0 -> S0 * AP console: poweroff Reulst: S0 -> G3 * Short power press to power-on: $ dut-control dut-control power_key:tab Result: G3 -> S0 BRANCH=none Change-Id: Iacaa3dbcdafd61b2f3371e2ba376ebdcf29659ff Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4269797 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* mt8186,mt8188: disable IN_AP_SUSPEND interrupt in G3/S5Eric Yilun Lin2023-02-211-12/+6
| | | | | | | | | | | | | | | | | | | GPIO_AP_IN_SLEEP_L will be floating when the AP off, so only enable the interrupt when AP is on. Also, drop the unnecessary interrupt enables, which should have done in power_common_init(). BUG=none TEST=AP suspend, and AP_IN_SLEEP_L is captured by the powerindebug BRANCH=none Change-Id: I496c2a4a0b7d7e2f18d8c14945f67d91878ac045 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4269796 Commit-Queue: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Eric Yilun Lin <yllin@google.com>
* mt8186,mt8188: check IN_AP_RST signal when wachdog IRQ raisedEric Yilun Lin2023-02-211-5/+2
| | | | | | | | | | | | | | | | | Watchdog interrupt is only significant only when AP is on, which means the IN_AP_RST should not be asserted. BUG=b:242012415 TEST=stop daisydog; echo > /dev/watchdog; EC report AP_WACHDOG reset BRANCH=none LOW_COVERAGE_REASON=initial bringup Change-Id: I2af6fc6f61b909a31e542d86a5a43011cdb6afac Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3820873 Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* power/mt8186: support mt8188 power sequenceEric Yilun Lin2023-02-101-13/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MT8186 and MT8188 chipset have similar power sequence, so we re-use the mt8186.c. Add power signal EN_PP4200_PG_S5, which controls the PP4200 rail and which is PMIC's VCC. We turn it on/off at S5->S3/S3->S5. Also, drop cros-ec support, which is not used. BUG=b:267268982 TEST=* Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control dut-control power_key:9.2 Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control dut-control power_key:9.2 Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control dut-control power_key:tab Result: G3 -> S0 * Console command: apreset Result: S0 -> S0, AP reboots * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 BRANCH=none Change-Id: I76bf3e4c4352982132e37bf952c29c4fce60f630 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4219278 Commit-Queue: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com>
* corsola: power sequence teststabilize-15300.B-mainTing Shen2022-12-301-10/+0
| | | | | | | | | | | | | | | | | | Add a test to verify mt8186 power state machine behavior. power/mt8186.c has above 90% coverage after this CL. BUG=b:256575497 TEST=./twister -v -i --coverage -p native_posix -p unit_testing BRANCH=none Change-Id: I2f274697e83dfc50f6976b8f6d137df6c69da2b9 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4127103 Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* power/mt8186: implement ap-idle flagTing Shen2022-10-311-0/+8
| | | | | | | | | | | | | | | | | When EC_RESET_FLAG_AP_IDLE appears, ec should keep the existing power state. BUG=b:256085410 TEST=manually BRANCH=corsola Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I1dd0afc6dc9a9c8a24f19f6dc6877b81d214bd32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3992832 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Code-Coverage: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org>
* Update license boilerplate text in source code filesMike Frysinger2022-09-121-1/+1
| | | | | | | | | | | | | | | Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* power/mt8186: remove redundant msleepTing Shen2022-08-151-1/+0
| | | | | | | | | | | | | | | | | | | | | The original purpose of msleep(500) line is to wait for pmic ready, it was added in CL:3233783 ps30. After a few code changes, another power_wait_mask_signals_timeout line was added to provide the same functionality. Now we are waiting for pmic twice, we should remove the duplicated msleep call. BUG=b:237249144 TEST=manually BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I15e3930cf07c0ce6c225f61727e0566a0644e32a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3831159 Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org>
* util: remove unused includesYuval Peress2022-08-051-1/+1
| | | | | | | | | | | | | | | | Remove these includes as they're not needed in this header. Instead, the includes should go where they're actually being used. BRANCH=none BUG=b:240574048 TEST=make buildall -j TEST=zmake build -a Signed-off-by: Yuval Peress <peress@google.com> Change-Id: I64b10af3216654b2a20caa1cabd267661a0bca39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3791980 Reviewed-by: Tristan Honscheid <honscheid@google.com> Commit-Queue: Tristan Honscheid <honscheid@google.com>
* power/mt8186: add CHIPSET_SUSPEND_COMPLETE hookTing Shen2022-07-141-0/+2
| | | | | | | | | | | | | | | | | | | | | CHIPSET_RESUME_INIT is usually paired with SUSPEND_COMPLETE (for example: chip/npcx/shi.c). Since we enabled RESUME_INIT on MT8186, we must invoke CHIPSET_SUSPEND_COMPLETE callback when entering S3 too. BUG=b:215659327 TEST=EC power consumption back to 4mw BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I649b7f50aedbd77ea1954fc31295910f08e24cb8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759110 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Joyce Lee <lyunjie@google.com> Tested-by: Joyce Lee <lyunjie@google.com>
* mt8186: reports reset/shutdown reason in hexEric Yilun Lin2022-07-071-2/+2
| | | | | | | | | | | | | | | It's more readable if the reason is in hex format. BUG=none TEST=the reasons are reports in hex format BRANCH=none Change-Id: I95133806caad9047dcbbffc22b8c1f04033773d8 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750274 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* mt8186: reports forcing shutdown by long pwrkey pressEric Yilun Lin2022-07-071-5/+14
| | | | | | | | | | | | | | | | | | | | | | | When powerkey long pressed for 8(+-20%) seconds, the PMIC will enter forcing shutdown mode and turn off the rail. If PMIC enters the forcing shutdown process too fast, then the shutdown reason report will be canceled, and we won't know the exactly shutdown reason. This CL reports the shutdown reason when the power is going for S0S3, and hasn't reported the reason. BUG=none TEST=1. at S0, ensure the long powerkey press reports 0x8009 2. apshutdown works 3. shutdown from AP works 4. at S3, long press powerkey: S3->S0->S3->S5->G3 BRANCH=none Change-Id: I1ea8e710a81ed7267c7f87c6c6d711a045603b7e Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750273 Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* power/mt8186: fix the init value of is_exiting_offTing Shen2022-07-051-3/+8
| | | | | | | | | | | | | | | | | | | | is_exiting_off means that EC wants to leave S5/G3. If EC is already in S0 during initialization, this flag should be false. BUG=b:237499922 TEST=1) `reboot ro` 2) wait until device reaches S0 3) `sysjump rw` 4) `apshutdown` make sure AP stays at G3 BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ibac81cd5d1b62d153fc9aa77d33e04754bb0db9a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3735621 Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* power/mt8186.c: Format with clang-formatJack Rosenthal2022-07-011-11/+10
| | | | | | | | | | | BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic24fcef55f8a7dfcfcab827a0b32a73cae41323c Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727064 Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* corsola: Enable CHIPSET_RESUME_INIT hook configurationlschyi2022-06-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable CHIPSET_RESUME_INIT hook on mt8186 platform and corsola, and trigger it from S3 -> S0. BUG=b:229810117 TEST=Check the operation mode register (0x00) entering/leaving S3: (1) USB 3 device is connected, register value not changed with different type c side. (2) USB 2 device is connected, only the USB mode bit is unset at S3, and set in S0. (3) USB 2 device is connected in S0, and remove the device when in S3. USB mode bit is unset after back to S0. (4) Connect a A->C adapter in S0, then insert USB 2/3 device in S3. The USB mode bit is set after leaving S3. `lsusb` can identify the device under USB 2/3 bus. (5) USB mode bit is always unset if no device is connected. (6) type c display is connected, register value not changed. BRANCH=None Signed-off-by: lschyi <lschyi@google.com> Change-Id: Ic7bfcbc401e5e94d2cc8f2ec7d39c5801daaf0b5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3707068 Tested-by: Sung-Chi Li <lschyi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Sung-Chi Li <lschyi@chromium.org>
* power/mt8186: delay HOOK_CHIPSET_SHUTDOWN_COMPLETE to S5G3.Eric Yilun Lin2022-05-301-1/+9
| | | | | | | | | | | | | | | | | | | | Normally, HOOK_CHIPSET_SHUTDOWN_COMLETE is called in S3S5, but on Mediatek platform, if it's a shutdown triggered by EC side, then EC is unable to set up PMIC registers for a graceful shutdown. What we can do instead is a force shutdown by asserting EC_PMIC_EN_ODL for 8 seconds, and all the rails are forced off, and the system will enter G3 after EC_PMIC_EN_ODL is released. BUG=b:233988259 TEST=hibernate at S0, and ensure the system enter G3 before hiberate BRANCH=none Change-Id: I8cbc5ad979b6b2fe074b7fd6167d484109a40aa4 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3676899 Tested-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* power/mt8186: stay at S5 before PMIC is fully offEric Yilun Lin2022-05-301-10/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we command the device to enter hibernate mode before PMIC is fully off, then there will be power leakage from AP_EC_WDTRST_L which is pulled up by PMIC. On MT8186, the S5 was a transition state, it passed through S5 and entered G3 before the PMIC is fully off. In normal cases, this won't be an issue that it takes long enough time to hibernate from G3. However, firmware_ECWakeFromULP force EC enter hibernation once the DUT gets into the G3, and this hits the PMIC issue. To fix this, we force the DUT staying at S5 until the EC_PMIC_EN_ODL released (8 seconds), and then enter the G3 state. BUG=b:233988259 TEST=stay at S5 until EC_PMIC_EN_ODL deasserted and then into G3. TEST=Test following items: * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control 'ec_uart_cmd:powerbtn 8200' Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control 'ec_uart_cmd:powerbtn 8200' Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control 'ec_uart_cmd:powerbtn 200' Result: G3 -> S0 * Console command: apreset Result: S0 -> S5 -> S0, AP reboots * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 BRANCH=none Change-Id: Id5809ff5dc72e35a75d9b20b2013522610ae4eaf Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3676896 Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* power: Add chipset and board callbacks for sleep hangsRob Barnes2022-03-171-2/+3
| | | | | | | | | | | | | | | | | | Instead of passing a callback to host_sleep, define overridable board and chipset callbacks for sleep hang detection. Introduce a sleep_hang_type enum that identifies the type of sleep hang (suspend or resume). These changes make it eaier for boards to implement custom logic to handle sleep hangs. BUG=b:218892808 BRANCH=guybrush TEST=Observe suspend hang detection on Nipperkin with KI Change-Id: Ifacf90f808b1447633f7cfc2d570209d1e233950 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3529606 Reviewed-by: Diana Z <dzigterman@chromium.org>
* mt8186: enable AP watchdog interruptEric Yilun Lin2022-02-211-2/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reset AP (S0->S0) when AP watchdog interrupt is raised. Note that we should only do watchdog reset when it's a real WDT. A real WDT is that AP_WDTRST_L is the first power signal asserted, otherwise it's a fake WDT. Warm resets, AP shutdown will cause a fake WDT because when they are resetting the chipset, the WDT signal will be asserted in the process. BUG=b:218420108 TEST=in EC console apshutdown : S0->G3 apreset : S0->S0 lid open : G3->S0 toggle cold reset: G3->S0 powerbtn 8.2s : S0->G3 in AP console ectool apreset : S0->S0 shutdown : S0->G3 stop daisydog; echo > /dev/watchdog: S0->S0 reboot : S0->S0 BRANCH=none Change-Id: Ic0360c1eff1cf25d7a28974d76af41dd0c2984cd Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3459589 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Eric Yilun Lin <yllin@google.com> Auto-Submit: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* power: add mt8186 power sequenceTing Shen2022-01-071-0/+410
MT8186 power sequence is a simplified version of 8192/95. EC does not lie between AP and PMIC, so there's no need to forward the signals. Other logics are almost the same. BUG=b:206338930 TEST=Test following items on krabby CL:3233784 * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control 'ec_uart_cmd:powerbtn 8200' Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control 'ec_uart_cmd:powerbtn 8200' Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control 'ec_uart_cmd:powerbtn 200' Result: G3 -> S0 * Console command: apreset Result: S0 -> S5 -> S0, AP reboots * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 BRANCH=none Cq-Depend: chromium:3366102 Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Iebfe77c8f6d127ee4d0685903b67afd215ca6682 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3233783 Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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