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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Register map for MEC1322 processor
*/
#ifndef __CROS_EC_REGISTERS_H
#define __CROS_EC_REGISTERS_H
#include "common.h"
/* EC Chip Configuration */
#define MEC1322_CHIP_BASE 0x400fff00
#define MEC1322_CHIP_DEV_ID REG8(MEC1322_CHIP_BASE + 0x20)
#define MEC1322_CHIP_DEV_REV REG8(MEC1322_CHIP_BASE + 0x21)
/* Power/Clocks/Resets */
#define MEC1322_PCR_BASE 0x40080100
#define MEC1322_PCR_CHIP_SLP_EN REG32(MEC1322_PCR_BASE + 0x0)
#define MEC1322_PCR_CHIP_CLK_REQ REG32(MEC1322_PCR_BASE + 0x4)
#define MEC1322_PCR_EC_SLP_EN REG32(MEC1322_PCR_BASE + 0x8)
#define MEC1322_PCR_EC_CLK_REQ REG32(MEC1322_PCR_BASE + 0xc)
#define MEC1322_PCR_HOST_SLP_EN REG32(MEC1322_PCR_BASE + 0x10)
#define MEC1322_PCR_HOST_CLK_REQ REG32(MEC1322_PCR_BASE + 0x14)
#define MEC1322_PCR_SYS_SLP_CTL REG32(MEC1322_PCR_BASE + 0x18)
#define MEC1322_PCR_PROC_CLK_CTL REG32(MEC1322_PCR_BASE + 0x20)
#define MEC1322_PCR_EC_SLP_EN2 REG32(MEC1322_PCR_BASE + 0x24)
#define MEC1322_PCR_EC_CLK_REQ2 REG32(MEC1322_PCR_BASE + 0x28)
#define MEC1322_PCR_SLOW_CLK_CTL REG32(MEC1322_PCR_BASE + 0x2c)
#define MEC1322_PCR_CHIP_OSC_ID REG32(MEC1322_PCR_BASE + 0x30)
#define MEC1322_PCR_CHIP_PWR_RST REG32(MEC1322_PCR_BASE + 0x34)
#define MEC1322_PCR_CHIP_RST_EN REG32(MEC1322_PCR_BASE + 0x38)
#define MEC1322_PCR_HOST_RST_EN REG32(MEC1322_PCR_BASE + 0x3c)
#define MEC1322_PCR_EC_RST_EN REG32(MEC1322_PCR_BASE + 0x40)
#define MEC1322_PCR_EC_RST_EN2 REG32(MEC1322_PCR_BASE + 0x44)
#define MEC1322_PCR_PWR_RST_CTL REG32(MEC1322_PCR_BASE + 0x48)
/* EC Subsystem */
#define MEC1322_EC_BASE 0x4000fc00
#define MEC1322_EC_INT_CTRL REG32(MEC1322_EC_BASE + 0x18)
/* Interrupt aggregator */
#define MEC1322_INT_BASE 0x4000c000
#define MEC1322_INTx_BASE(x) (MEC1322_INT_BASE + ((x) - 8) * 0x14)
#define MEC1322_INT_SOURCE(x) REG32(MEC1322_INTx_BASE(x) + 0x0)
#define MEC1322_INT_ENABLE(x) REG32(MEC1322_INTx_BASE(x) + 0x4)
#define MEC1322_INT_RESULT(x) REG32(MEC1322_INTx_BASE(x) + 0x8)
#define MEC1322_INT_DISABLE(x) REG32(MEC1322_INTx_BASE(x) + 0xc)
#define MEC1322_INT_BLK_EN REG32(MEC1322_INT_BASE + 0x200)
#define MEC1322_INT_BLK_DIS REG32(MEC1322_INT_BASE + 0x204)
#define MEC1322_INT_BLK_IRQ REG32(MEC1322_INT_BASE + 0x208)
/* UART */
#define MEC1322_UART_CONFIG_BASE 0x400f1f00
#define MEC1322_UART_RUNTIME_BASE 0x400f1c00
#define MEC1322_UART_ACT REG8(MEC1322_UART_CONFIG_BASE + 0x30)
#define MEC1322_UART_CFG REG8(MEC1322_UART_CONFIG_BASE + 0xf0)
/* DLAB=0 */
#define MEC1322_UART_RB /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
#define MEC1322_UART_TB /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
#define MEC1322_UART_IER REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
/* DLAB=1 */
#define MEC1322_UART_PBRG0 REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
#define MEC1322_UART_PBRG1 REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
#define MEC1322_UART_FCR /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2)
#define MEC1322_UART_IIR /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2)
#define MEC1322_UART_LCR REG8(MEC1322_UART_RUNTIME_BASE + 0x3)
#define MEC1322_UART_MCR REG8(MEC1322_UART_RUNTIME_BASE + 0x4)
#define MEC1322_UART_LSR REG8(MEC1322_UART_RUNTIME_BASE + 0x5)
#define MEC1322_UART_MSR REG8(MEC1322_UART_RUNTIME_BASE + 0x6)
#define MEC1322_UART_SCR REG8(MEC1322_UART_RUNTIME_BASE + 0x7)
/* GPIO */
#define MEC1322_GPIO_BASE 0x40081000
#define MEC1322_GPIO_PORT(x) (x)
#define GPIO_PORT(x) MEC1322_GPIO_PORT(x)
static inline uintptr_t gpio_port_base(int port_id)
{
int oct = (port_id / 10) * 8 + port_id % 10;
return MEC1322_GPIO_BASE + oct * 0x20;
}
#define MEC1322_GPIO_CTL(port, id) REG32(gpio_port_base(port) + (id << 2))
#define DUMMY_GPIO_BANK GPIO_PORT(0)
/* Timer */
#define MEC1322_TMR16_BASE(x) (0x40000c00 + (x) * 0x20)
#define MEC1322_TMR32_BASE(x) (0x40000c80 + (x) * 0x20)
#define MEC1322_TMR16_CNT(x) REG32(MEC1322_TMR16_BASE(x) + 0x0)
#define MEC1322_TMR16_PRE(x) REG32(MEC1322_TMR16_BASE(x) + 0x4)
#define MEC1322_TMR16_STS(x) REG32(MEC1322_TMR16_BASE(x) + 0x8)
#define MEC1322_TMR16_IEN(x) REG32(MEC1322_TMR16_BASE(x) + 0xc)
#define MEC1322_TMR16_CTL(x) REG32(MEC1322_TMR16_BASE(x) + 0x10)
#define MEC1322_TMR32_CNT(x) REG32(MEC1322_TMR32_BASE(x) + 0x0)
#define MEC1322_TMR32_PRE(x) REG32(MEC1322_TMR32_BASE(x) + 0x4)
#define MEC1322_TMR32_STS(x) REG32(MEC1322_TMR32_BASE(x) + 0x8)
#define MEC1322_TMR32_IEN(x) REG32(MEC1322_TMR32_BASE(x) + 0xc)
#define MEC1322_TMR32_CTL(x) REG32(MEC1322_TMR32_BASE(x) + 0x10)
/* Watchdog */
#define MEC1322_WDG_BASE 0x40000400
#define MEC1322_WDG_LOAD REG16(MEC1322_WDG_BASE + 0x0)
#define MEC1322_WDG_CTL REG8(MEC1322_WDG_BASE + 0x4)
#define MEC1322_WDG_KICK REG8(MEC1322_WDG_BASE + 0x8)
#define MEC1322_WDG_CNT REG16(MEC1322_WDG_BASE + 0xc)
/* VBAT */
#define MEC1322_VBAT_BASE 0x4000a400
#define MEC1322_VBAT_STS REG32(MEC1322_VBAT_BASE + 0x0)
#define MEC1322_VBAT_CE REG32(MEC1322_VBAT_BASE + 0x8)
#define MEC1322_VBAT_RAM(x) REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x))
/* LPC */
#define MEC1322_LPC_CFG_BASE 0x400f3300
#define MEC1322_LPC_ACT REG8(MEC1322_LPC_CFG_BASE + 0x30)
#define MEC1322_LPC_SIRQ(x) REG8(MEC1322_LPC_CFG_BASE + 0x40 + (x))
#define MEC1322_LPC_CFG_BAR REG32(MEC1322_LPC_CFG_BASE + 0x60)
#define MEC1322_LPC_EMI_BAR REG32(MEC1322_LPC_CFG_BASE + 0x64)
#define MEC1322_LPC_UART_BAR REG32(MEC1322_LPC_CFG_BASE + 0x68)
#define MEC1322_LPC_8042_BAR REG32(MEC1322_LPC_CFG_BASE + 0x78)
#define MEC1322_LPC_ACPI_EC0_BAR REG32(MEC1322_LPC_CFG_BASE + 0x88)
#define MEC1322_LPC_ACPI_EC1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x8c)
#define MEC1322_LPC_ACPI_PM1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x90)
#define MEC1322_LPC_PORT92_BAR REG32(MEC1322_LPC_CFG_BASE + 0x94)
#define MEC1322_LPC_MAILBOX_BAR REG32(MEC1322_LPC_CFG_BASE + 0x98)
#define MEC1322_LPC_RTC_BAR REG32(MEC1322_LPC_CFG_BASE + 0x9c)
#define MEC1322_LPC_MEM_BAR REG32(MEC1322_LPC_CFG_BASE + 0xa0)
#define MEC1322_LPC_MEM_BAR_CFG REG32(MEC1322_LPC_CFG_BASE + 0xa4)
#define MEC1322_LPC_RT_BASE 0x400f3100
#define MEC1322_LPC_MEM_HOST_CFG REG32(MEC1322_LPC_RT_BASE + 0xfc)
/* EMI */
#define MEC1322_EMI_BASE 0x400f0100
#define MEC1322_EMI_H2E_MBX REG8(MEC1322_EMI_BASE + 0x0)
#define MEC1322_EMI_E2H_MBX REG8(MEC1322_EMI_BASE + 0x1)
#define MEC1322_EMI_MBA0 REG32(MEC1322_EMI_BASE + 0x4)
#define MEC1322_EMI_MRL0 REG16(MEC1322_EMI_BASE + 0x8)
#define MEC1322_EMI_MWL0 REG16(MEC1322_EMI_BASE + 0xa)
#define MEC1322_EMI_MBA1 REG32(MEC1322_EMI_BASE + 0xc)
#define MEC1322_EMI_MRL1 REG16(MEC1322_EMI_BASE + 0x10)
#define MEC1322_EMI_MWL1 REG16(MEC1322_EMI_BASE + 0x12)
#define MEC1322_EMI_ISR REG16(MEC1322_EMI_BASE + 0x14)
#define MEC1322_EMI_HCE REG16(MEC1322_EMI_BASE + 0x16)
#define MEC1322_EMI_RT_BASE 0x400f0000
#define MEC1322_EMI_ISR_B0 REG8(MEC1322_EMI_RT_BASE + 0x8)
#define MEC1322_EMI_ISR_B1 REG8(MEC1322_EMI_RT_BASE + 0x9)
#define MEC1322_EMI_IMR_B0 REG8(MEC1322_EMI_RT_BASE + 0xa)
#define MEC1322_EMI_IMR_B1 REG8(MEC1322_EMI_RT_BASE + 0xb)
/* Mailbox */
#define MEC1322_MBX_BASE 0x400f2500
#define MEC1322_MBX_H2E_MBX REG8(MEC1322_MBX_BASE + 0x0)
#define MEC1322_MBX_E2H_MBX REG8(MEC1322_MBX_BASE + 0x4)
#define MEC1322_MBX_ISR REG8(MEC1322_MBX_BASE + 0x8)
#define MEC1322_MBX_IMR REG8(MEC1322_MBX_BASE + 0xc)
#define MEC1322_MBX_REG(x) REG8(MEC1322_MBX_BASE + 0x10 + (x))
/* IRQ Numbers */
#define MEC1322_IRQ_I2C_0 0
#define MEC1322_IRQ_I2C_1 1
#define MEC1322_IRQ_I2C_2 2
#define MEC1322_IRQ_I2C_3 3
#define MEC1322_IRQ_DMA_0 4
#define MEC1322_IRQ_DMA_1 5
#define MEC1322_IRQ_DMA_2 6
#define MEC1322_IRQ_DMA_3 7
#define MEC1322_IRQ_DMA_4 8
#define MEC1322_IRQ_DMA_5 9
#define MEC1322_IRQ_DMA_6 10
#define MEC1322_IRQ_DMA_7 11
#define MEC1322_IRQ_LPC 12
#define MEC1322_IRQ_UART 13
#define MEC1322_IRQ_EMI 14
#define MEC1322_IRQ_ACPIEC0_IBF 15
#define MEC1322_IRQ_ACPIEC0_OBF 16
#define MEC1322_IRQ_ACPIEC1_IBF 17
#define MEC1322_IRQ_ACPIEC1_OBF 18
#define MEC1322_IRQ_ACPIPM1_CTL 19
#define MEC1322_IRQ_ACPIPM1_EN 20
#define MEC1322_IRQ_ACPIPM1_STS 21
#define MEC1322_IRQ_8042EM_OBF 22
#define MEC1322_IRQ_8042EM_IBF 23
#define MEC1322_IRQ_MAILBOX 24
#define MEC1322_IRQ_PECI_HOST 25
#define MEC1322_IRQ_TACH_0 26
#define MEC1322_IRQ_TACH_1 27
#define MEC1322_IRQ_ADC_SNGL 28
#define MEC1322_IRQ_ADC_RPT 29
#define MEC1322_IRQ_PS2_0 32
#define MEC1322_IRQ_PS2_1 33
#define MEC1322_IRQ_PS2_2 34
#define MEC1322_IRQ_PS2_3 35
#define MEC1322_IRQ_SPI0_TX 36
#define MEC1322_IRQ_SPI0_RX 37
#define MEC1322_IRQ_HTIMER 38
#define MEC1322_IRQ_KSC_INT 39
#define MEC1322_IRQ_MAILBOX_DATA 40
#define MEC1322_IRQ_TIMER16_0 49
#define MEC1322_IRQ_TIMER16_1 50
#define MEC1322_IRQ_TIMER16_2 51
#define MEC1322_IRQ_TIMER16_3 52
#define MEC1322_IRQ_TIMER32_0 53
#define MEC1322_IRQ_TIMER32_1 54
#define MEC1322_IRQ_SPI1_TX 55
#define MEC1322_IRQ_SPI1_RX 56
#define MEC1322_IRQ_GIRQ8 57
#define MEC1322_IRQ_GIRQ9 58
#define MEC1322_IRQ_GIRQ10 59
#define MEC1322_IRQ_GIRQ11 60
#define MEC1322_IRQ_GIRQ12 61
#define MEC1322_IRQ_GIRQ13 62
#define MEC1322_IRQ_GIRQ14 63
#define MEC1322_IRQ_GIRQ15 64
#define MEC1322_IRQ_GIRQ16 65
#define MEC1322_IRQ_GIRQ17 66
#define MEC1322_IRQ_GIRQ18 67
#define MEC1322_IRQ_GIRQ19 68
#define MEC1322_IRQ_GIRQ20 69
#define MEC1322_IRQ_GIRQ21 70
#define MEC1322_IRQ_GIRQ22 71
#define MEC1322_IRQ_GIRQ23 72
#define MEC1322_IRQ_DMA_8 81
#define MEC1322_IRQ_DMA_9 82
#define MEC1322_IRQ_DMA_10 83
#define MEC1322_IRQ_DMA_11 84
#define MEC1322_IRQ_PWM_WDT3 85
#define MEC1322_IRQ_RTC 91
#define MEC1322_IRQ_RTC_ALARM 92
#endif /* __CROS_EC_REGISTERS_H */
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