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# Copyright 2021 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# This file defines the correct defaults when using the NPCX7 series chipset
#
if SOC_SERIES_NPCX7
if SOC_NPCX7M6FC
#
# NPCX796FC: 512 KiB Flash, 192 KiB code RAM, 62 KiB data RAM
#
# Code RAM base for NPCX796FC
config CROS_EC_PROGRAM_MEMORY_BASE
default 0x10090000
config CROS_EC_RAM_BASE
default 0x200c0000
config CROS_EC_DATA_RAM_SIZE
default 0x00010000
config CROS_EC_RAM_SIZE
default 0x0000f800
config FLASH_SIZE
default 512
config CROS_EC_RO_MEM_OFF
default 0x0
# Image size limited by code RAM size (192 KiB)
config CROS_EC_RO_SIZE
default 0x30000
# RW firmware in program memory - Identical to RO, only one image loaded at a
# time.
config CROS_EC_RW_MEM_OFF
default 0x0
config CROS_EC_RW_SIZE
default 0x30000
endif # SOC_NPCX7M6FC
if SOC_NPCX7M7FC
#
# NPCX797FC: 512 KiB Flash, 320 KiB code RAM, 62 KiB data RAM
#
# Code RAM base for NPCX797FC
config CROS_EC_PROGRAM_MEMORY_BASE
default 0x10070000
config CROS_EC_RAM_BASE
default 0x200c0000
config CROS_EC_DATA_RAM_SIZE
default 0x00010000
config CROS_EC_RAM_SIZE
default 0x0000f800
config FLASH_SIZE
default 512
config CROS_EC_RO_MEM_OFF
default 0x0
# Image size limited by 1/2 Flash size (256 KiB)
config CROS_EC_RO_SIZE
default 0x40000
# RW firmware in program memory - Identical to RO, only one image loaded at a
# time.
config CROS_EC_RW_MEM_OFF
default 0x0
config CROS_EC_RW_SIZE
default 0x40000
endif # SOC_NPCX7M7FC
endif # SOC_SERIES_NPCX7
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