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authorArthur Heymans <arthur@aheymans.xyz>2019-10-23 17:25:58 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-11-01 11:44:51 +0000
commit340e4b80904feb6c5c21497fc52966854fa5ee79 (patch)
tree4026de0ec0cc41f51dd121a0be76642a8d0a286d
parent44874482fec69a849b06c378aa3eb69e75425256 (diff)
downloadcoreboot-340e4b80904feb6c5c21497fc52966854fa5ee79.tar.gz
lib/cbmem_top: Add a common cbmem_top implementation
This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
-rw-r--r--src/arch/x86/cbmem.c2
-rw-r--r--src/cpu/amd/family_10h-family_15h/ram_calc.c2
-rw-r--r--src/cpu/ti/am335x/cbmem.c2
-rw-r--r--src/include/cbmem.h11
-rw-r--r--src/lib/Kconfig6
-rw-r--r--src/lib/imd_cbmem.c23
-rw-r--r--src/mainboard/emulation/qemu-aarch64/cbmem.c2
-rw-r--r--src/mainboard/emulation/qemu-armv7/cbmem.c2
-rw-r--r--src/mainboard/emulation/qemu-i440fx/memmap.c2
-rw-r--r--src/mainboard/emulation/qemu-power8/cbmem.c2
-rw-r--r--src/northbridge/intel/e7505/memmap.c2
-rw-r--r--src/northbridge/intel/fsp_rangeley/memmap.c2
-rw-r--r--src/northbridge/intel/gm45/memmap.c2
-rw-r--r--src/northbridge/intel/haswell/memmap.c2
-rw-r--r--src/northbridge/intel/i440bx/memmap.c2
-rw-r--r--src/northbridge/intel/i945/memmap.c2
-rw-r--r--src/northbridge/intel/nehalem/memmap.c2
-rw-r--r--src/northbridge/intel/pineview/memmap.c2
-rw-r--r--src/northbridge/intel/sandybridge/memmap.c2
-rw-r--r--src/northbridge/intel/x4x/memmap.c2
-rw-r--r--src/northbridge/via/vx900/memmap.c2
-rw-r--r--src/soc/amd/picasso/memmap.c2
-rw-r--r--src/soc/amd/stoneyridge/memmap.c2
-rw-r--r--src/soc/cavium/cn81xx/cbmem.c2
-rw-r--r--src/soc/imgtec/pistachio/cbmem.c2
-rw-r--r--src/soc/intel/apollolake/memmap.c2
-rw-r--r--src/soc/intel/baytrail/memmap.c2
-rw-r--r--src/soc/intel/braswell/memmap.c2
-rw-r--r--src/soc/intel/broadwell/memmap.c2
-rw-r--r--src/soc/intel/cannonlake/memmap.c2
-rw-r--r--src/soc/intel/denverton_ns/memmap.c2
-rw-r--r--src/soc/intel/fsp_baytrail/memmap.c2
-rw-r--r--src/soc/intel/fsp_broadwell_de/memmap.c2
-rw-r--r--src/soc/intel/icelake/memmap.c2
-rw-r--r--src/soc/intel/quark/memmap.c2
-rw-r--r--src/soc/intel/skylake/memmap.c2
-rw-r--r--src/soc/mediatek/common/cbmem.c2
-rw-r--r--src/soc/nvidia/tegra124/cbmem.c2
-rw-r--r--src/soc/nvidia/tegra210/cbmem.c2
-rw-r--r--src/soc/qualcomm/ipq40xx/cbmem.c2
-rw-r--r--src/soc/qualcomm/ipq806x/cbmem.c2
-rw-r--r--src/soc/qualcomm/qcs405/cbmem.c2
-rw-r--r--src/soc/qualcomm/sc7180/cbmem.c2
-rw-r--r--src/soc/qualcomm/sdm845/cbmem.c2
-rw-r--r--src/soc/rockchip/common/cbmem.c2
-rw-r--r--src/soc/samsung/exynos5250/cbmem.c2
-rw-r--r--src/soc/samsung/exynos5420/cbmem.c2
-rw-r--r--src/soc/sifive/fu540/cbmem.c2
-rw-r--r--src/soc/ucb/riscv/cbmem.c2
49 files changed, 86 insertions, 46 deletions
diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
index 16c35b5dea..f7c58a47ce 100644
--- a/src/arch/x86/cbmem.c
+++ b/src/arch/x86/cbmem.c
@@ -16,7 +16,7 @@
#if CONFIG(CBMEM_TOP_BACKUP)
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
static void *cbmem_top_backup;
void *top_backup;
diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c
index 3946b67b2d..a1dc1f4ba6 100644
--- a/src/cpu/amd/family_10h-family_15h/ram_calc.c
+++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c
@@ -86,7 +86,7 @@ uint64_t get_cc6_memory_size()
return cc6_size;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uint32_t topmem = rdmsr(TOP_MEM).lo;
diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c
index a626ec6adf..2ecca65551 100644
--- a/src/cpu/ti/am335x/cbmem.c
+++ b/src/cpu/ti/am335x/cbmem.c
@@ -15,7 +15,7 @@
#include <cbmem.h>
#include <symbols.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return _dram + (CONFIG_DRAM_SIZE_MB << 20);
}
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 4005fa205a..a22c420ad3 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -73,7 +73,18 @@ void cbmem_top_init(void);
* below 4GiB for 32bit coreboot builds. On 64bit coreboot builds there's no
* upper limit. This should not be called before memory is initialized.
*/
+/* The assumption is made that the result of cbmem_top_romstage fits in the size
+ of uintptr_t in the ramstage. */
+extern uintptr_t _cbmem_top_ptr;
void *cbmem_top(void);
+/* With CONFIG_RAMSTAGE_CBMEM_TOP_ARG set, the result of cbmem_top is passed via
+ * calling arguments to the next stage and saved in the global _cbmem_top_ptr
+ * global variable. Only a romstage callback needs to be implemented by the
+ * platform. It is up to the stages after romstage to save the calling argument
+ * in the _cbmem_top_ptr symbol. Without CONFIG_RAMSTAGE_CBMEM_TOP_ARG the same
+ * implementation as used in romstage will be used.
+ */
+void *cbmem_top_chipset(void);
/* Add a cbmem entry of a given size and id. These return NULL on failure. The
* add function performs a find first and do not check against the original
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index cb1e4a5cc8..b94ac495b7 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -24,6 +24,12 @@ config RAMSTAGE_LIBHWBASE
help
Selected by features that require `libhwbase` in ramstage.
+config RAMSTAGE_CBMEM_TOP_ARG
+ bool
+ help
+ Select this if stages run after romstage get the cbmem_top
+ pointer as the function arguments when called from romstage.
+
config FLATTENED_DEVICE_TREE
bool
help
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index be135c22e8..cbd4b8f887 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <assert.h>
#include <boot/coreboot_tables.h>
#include <bootstate.h>
#include <bootmem.h>
@@ -44,6 +45,28 @@
(!CONFIG(ARCH_X86) || ENV_RAMSTAGE || ENV_POSTCAR || \
!CONFIG(CAR_GLOBAL_MIGRATION))
+/* The program loader passes on cbmem_top and the program entry point
+ has to fill in the _cbmem_top_ptr symbol based on the calling arguments. */
+uintptr_t _cbmem_top_ptr;
+
+void *cbmem_top(void)
+{
+ if (ENV_ROMSTAGE
+ || ((ENV_POSTCAR || ENV_RAMSTAGE)
+ && !CONFIG(RAMSTAGE_CBMEM_TOP_ARG))) {
+ MAYBE_STATIC_BSS void *top = NULL;
+ if (top)
+ return top;
+ top = cbmem_top_chipset();
+ return top;
+ }
+ if ((ENV_POSTCAR || ENV_RAMSTAGE) && CONFIG(RAMSTAGE_CBMEM_TOP_ARG))
+ return (void *)_cbmem_top_ptr;
+
+ dead_code();
+}
+
+
static inline struct imd *cbmem_get_imd(void)
{
if (CAN_USE_GLOBALS) {
diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c
index c50254df29..43894333e4 100644
--- a/src/mainboard/emulation/qemu-aarch64/cbmem.c
+++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c
@@ -10,7 +10,7 @@
#include <ramdetect.h>
#include <symbols.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
}
diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c
index 542e08d05e..143e11b88c 100644
--- a/src/mainboard/emulation/qemu-armv7/cbmem.c
+++ b/src/mainboard/emulation/qemu-armv7/cbmem.c
@@ -15,7 +15,7 @@
#include <symbols.h>
#include <ramdetect.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
}
diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c
index 8209379bef..098b3c2632 100644
--- a/src/mainboard/emulation/qemu-i440fx/memmap.c
+++ b/src/mainboard/emulation/qemu-i440fx/memmap.c
@@ -52,7 +52,7 @@ unsigned long qemu_get_memory_size(void)
return tomk;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t top = 0;
diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c
index 3df6b802e7..7d6d4a80d9 100644
--- a/src/mainboard/emulation/qemu-power8/cbmem.c
+++ b/src/mainboard/emulation/qemu-power8/cbmem.c
@@ -15,7 +15,7 @@
#include <cbmem.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
/* For now, last 1M of 4G */
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index c6a20fab9d..009db80215 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -21,7 +21,7 @@
#include <program_loading.h>
#include "e7505.h"
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
pci_devfn_t mch = PCI_DEV(0, 0, 0);
uintptr_t tolm;
diff --git a/src/northbridge/intel/fsp_rangeley/memmap.c b/src/northbridge/intel/fsp_rangeley/memmap.c
index da9ed71a67..275ddd3ac1 100644
--- a/src/northbridge/intel/fsp_rangeley/memmap.c
+++ b/src/northbridge/intel/fsp_rangeley/memmap.c
@@ -36,7 +36,7 @@ static uintptr_t smm_region_start(void)
return tom;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
}
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 7479a7834a..d34820eb3d 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -117,7 +117,7 @@ static size_t northbridge_get_tseg_size(void)
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
return (void *) top_of_ram;
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index 007a67d4b3..74d9292c14 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -34,7 +34,7 @@ static uintptr_t smm_region_start(void)
return tom & ~((1 << 20) - 1);
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *)smm_region_start();
}
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index 75a6c7e243..d260af6f32 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -23,7 +23,7 @@
#include <program_loading.h>
#include "i440bx.h"
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
/* Base of TSEG is top of usable DRAM */
/*
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 8207d06a55..000ac7e682 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -71,7 +71,7 @@ static size_t northbridge_get_tseg_size(void)
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
return (void *) top_of_ram;
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c
index 1c17b0d9b5..5de4b80acf 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/nehalem/memmap.c
@@ -42,7 +42,7 @@ static size_t northbridge_get_tseg_size(void)
return CONFIG_SMM_TSEG_SIZE;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *) smm_region_start();
}
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index b4fef6bc76..0aa70cdb34 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -132,7 +132,7 @@ static uintptr_t northbridge_get_tseg_base(void)
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
return (void *) top_of_ram;
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 67de34459b..99888fa2ae 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -31,7 +31,7 @@ static uintptr_t smm_region_start(void)
return tom;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *) smm_region_start();
}
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 41e491200b..1924ddf678 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -128,7 +128,7 @@ static uintptr_t northbridge_get_tseg_base(void)
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
return (void *) top_of_ram;
diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c
index d11dc65fd6..3121d7406e 100644
--- a/src/northbridge/via/vx900/memmap.c
+++ b/src/northbridge/via/vx900/memmap.c
@@ -120,7 +120,7 @@ u32 vx900_get_tolm(void)
return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t tolm;
uintptr_t fb_size;
diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c
index 09af7e4de7..82d6fb6e8e 100644
--- a/src/soc/amd/picasso/memmap.c
+++ b/src/soc/amd/picasso/memmap.c
@@ -58,7 +58,7 @@ void bert_reserved_region(void **start, size_t *size)
*size = BERT_REGION_MAX_SIZE;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
msr_t tom = rdmsr(TOP_MEM);
diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c
index 09af7e4de7..82d6fb6e8e 100644
--- a/src/soc/amd/stoneyridge/memmap.c
+++ b/src/soc/amd/stoneyridge/memmap.c
@@ -58,7 +58,7 @@ void bert_reserved_region(void **start, size_t *size)
*size = BERT_REGION_MAX_SIZE;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
msr_t tom = rdmsr(TOP_MEM);
diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c
index bb6fa18f20..a39bf4fe35 100644
--- a/src/soc/cavium/cn81xx/cbmem.c
+++ b/src/soc/cavium/cn81xx/cbmem.c
@@ -20,7 +20,7 @@
#include <stdlib.h>
#include <symbols.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
/* Make sure not to overlap with reserved ATF scratchpad */
return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB);
diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c
index 112df7ccc9..92bc1ce868 100644
--- a/src/soc/imgtec/pistachio/cbmem.c
+++ b/src/soc/imgtec/pistachio/cbmem.c
@@ -18,7 +18,7 @@
#include <stdlib.h>
#include <symbols.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return _dram + (CONFIG_DRAM_SIZE_MB << 20);
}
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index f828024d29..567ff1ebc6 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -20,7 +20,7 @@
#include "chip.h"
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
const config_t *config;
void *tolum = (void *)sa_get_tseg_base();
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c
index d9f6160dfc..e0aac9f423 100644
--- a/src/soc/intel/baytrail/memmap.c
+++ b/src/soc/intel/baytrail/memmap.c
@@ -29,7 +29,7 @@ static size_t smm_region_size(void)
return CONFIG_SMM_TSEG_SIZE;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *) smm_region_start();
}
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c
index d502aed9f9..e43c5469f6 100644
--- a/src/soc/intel/braswell/memmap.c
+++ b/src/soc/intel/braswell/memmap.c
@@ -33,7 +33,7 @@ void smm_region(uintptr_t *start, size_t *size)
*size = smm_region_size();
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t smm_base;
size_t smm_size;
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index f4a9d0ed24..ad50dd35db 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -41,7 +41,7 @@ static uintptr_t dpr_region_start(void)
return tom;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *) dpr_region_start();
}
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 475b8c79db..7a0d89717b 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -247,7 +247,7 @@ void cbmem_top_init(void)
* | |
* +-------------------------+
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
struct ebda_config ebda_cfg;
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index 9f788ddb41..b4761dbeef 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -60,7 +60,7 @@ u32 top_of_32bit_ram(void)
power_of_2(iqat_region_size + tseg_region_size);
}
-void *cbmem_top(void) { return (void *)top_of_32bit_ram(); }
+void *cbmem_top_chipset(void) { return (void *)top_of_32bit_ram(); }
static inline uintptr_t smm_region_start(void)
{
diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c
index 7fec7f9764..d8dcf49acb 100644
--- a/src/soc/intel/fsp_baytrail/memmap.c
+++ b/src/soc/intel/fsp_baytrail/memmap.c
@@ -40,7 +40,7 @@ static size_t smm_region_size(void)
* @return pointer to the first byte of reserved memory
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR);
}
diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c
index cbd3cf7788..96eb20502c 100644
--- a/src/soc/intel/fsp_broadwell_de/memmap.c
+++ b/src/soc/intel/fsp_broadwell_de/memmap.c
@@ -23,7 +23,7 @@
#include <soc/pci_devs.h>
#include <device/pci_ops.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR);
}
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index f17f255b13..76a8128520 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -226,7 +226,7 @@ void cbmem_top_init(void)
* | |
* +-------------------------+
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
struct ebda_config ebda_cfg;
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
index b8b85063a8..9ccaf55a1f 100644
--- a/src/soc/intel/quark/memmap.c
+++ b/src/soc/intel/quark/memmap.c
@@ -18,7 +18,7 @@
#include <cbmem.h>
#include <soc/reg_access.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uint32_t top_of_memory;
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 3aea1c31e6..09dc6e9f0d 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -248,7 +248,7 @@ void cbmem_top_init(void)
* | |
* +-------------------------+
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
struct ebda_config ebda_cfg;
diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c
index 8906565bd5..1a55d0113e 100644
--- a/src/soc/mediatek/common/cbmem.c
+++ b/src/soc/mediatek/common/cbmem.c
@@ -21,7 +21,7 @@
#define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB)
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS);
}
diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c
index 4b52a519bd..ac2a92e39d 100644
--- a/src/soc/nvidia/tegra124/cbmem.c
+++ b/src/soc/nvidia/tegra124/cbmem.c
@@ -17,7 +17,7 @@
#include <soc/display.h>
#include <soc/sdram.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL);
}
diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c
index 63ae497ebb..7fdde9e6ea 100644
--- a/src/soc/nvidia/tegra210/cbmem.c
+++ b/src/soc/nvidia/tegra210/cbmem.c
@@ -16,7 +16,7 @@
#include <cbmem.h>
#include <soc/addressmap.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
static uintptr_t addr;
diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c
index 05325cceb9..972c6258c9 100644
--- a/src/soc/qualcomm/ipq40xx/cbmem.c
+++ b/src/soc/qualcomm/ipq40xx/cbmem.c
@@ -23,7 +23,7 @@ void ipq_cbmem_backing_store_ready(void)
cbmem_backing_store_ready = 1;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
/*
* In romstage, make sure that cbmem backing store is ready before
diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c
index 9674db65da..6dc92a0c11 100644
--- a/src/soc/qualcomm/ipq806x/cbmem.c
+++ b/src/soc/qualcomm/ipq806x/cbmem.c
@@ -23,7 +23,7 @@ void ipq_cbmem_backing_store_ready(void)
cbmem_backing_store_ready = 1;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
/*
* In romstage, make sure that cbmem backing store is ready before
diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c
index e065409622..a780c6bcf1 100644
--- a/src/soc/qualcomm/qcs405/cbmem.c
+++ b/src/soc/qualcomm/qcs405/cbmem.c
@@ -15,7 +15,7 @@
#include <cbmem.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *)((uintptr_t)3 * GiB);
}
diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c
index 597e3692f8..fe81309c7a 100644
--- a/src/soc/qualcomm/sc7180/cbmem.c
+++ b/src/soc/qualcomm/sc7180/cbmem.c
@@ -15,7 +15,7 @@
#include <cbmem.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *)((uintptr_t)4 * GiB);
}
diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c
index 3b9ad4a617..b092a1a610 100644
--- a/src/soc/qualcomm/sdm845/cbmem.c
+++ b/src/soc/qualcomm/sdm845/cbmem.c
@@ -15,7 +15,7 @@
#include <cbmem.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *)((uintptr_t)4 * GiB);
}
diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c
index 401f8b2a65..6e3aabb81c 100644
--- a/src/soc/rockchip/common/cbmem.c
+++ b/src/soc/rockchip/common/cbmem.c
@@ -19,7 +19,7 @@
#include <stdlib.h>
#include <symbols.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB,
MAX_DRAM_ADDRESS);
diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c
index 1874495396..31463b19b5 100644
--- a/src/soc/samsung/exynos5250/cbmem.c
+++ b/src/soc/samsung/exynos5250/cbmem.c
@@ -17,7 +17,7 @@
#include <cbmem.h>
#include <soc/cpu.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *)(get_fb_base_kb() * KiB);
}
diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c
index e1999e888e..ffed589ee1 100644
--- a/src/soc/samsung/exynos5420/cbmem.c
+++ b/src/soc/samsung/exynos5420/cbmem.c
@@ -17,7 +17,7 @@
#include <soc/cpu.h>
#include <stddef.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *)(get_fb_base_kb() * KiB);
}
diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c
index 1c68de894b..a7de16c56a 100644
--- a/src/soc/sifive/fu540/cbmem.c
+++ b/src/soc/sifive/fu540/cbmem.c
@@ -19,7 +19,7 @@
#include <stdlib.h>
#include <symbols.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB,
FU540_MAXDRAM);
diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c
index 542e08d05e..143e11b88c 100644
--- a/src/soc/ucb/riscv/cbmem.c
+++ b/src/soc/ucb/riscv/cbmem.c
@@ -15,7 +15,7 @@
#include <symbols.h>
#include <ramdetect.h>
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
}