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| author | Sean Rhodes <sean@starlabs.systems> | 2023-05-03 21:15:24 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-11 16:54:13 +0000 |
| commit | 3b56cffa8a5508db3e36c84ae5142e471d1d8046 (patch) | |
| tree | 1304f7cb18348c225646b1c337bd92c60f160f02 | |
| parent | 8bf53c01620deeace3640b831d42d67f1d10e21b (diff) | |
| download | coreboot-3b56cffa8a5508db3e36c84ae5142e471d1d8046.tar.gz | |
soc/intel/apollolake: Only use 8 bits for afterg3
In GEN_PMCON1 (Offset 1020h), Bit 0 is the "After G3 Enable" (ag3e)
(source Intel document #569262). Only use 8 bits, in the same way as
most other Intel SOCs do, for pmc_soc_set_afterg3_en.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idb290d1480b03cb3425edc6ff29b9c78a6545df1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74955
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/apollolake/pmutil.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index b799d0253e..1ed90c1519 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -223,15 +223,16 @@ uint16_t get_pmbase(void) return (uint16_t)ACPI_BASE_ADDRESS; } +/* Set which power state system will be after reapplying the power (from G3 State) */ void pmc_soc_set_afterg3_en(const bool on) { - const uintptr_t gen_pmcon1 = soc_read_pmc_base() + GEN_PMCON1; - uint32_t reg32; + uint8_t reg8; + uint8_t *const pmcbase = pmc_mmio_regs(); - reg32 = read32p(gen_pmcon1); + reg8 = read8(pmcbase + GEN_PMCON_A); if (on) - reg32 &= ~SLEEP_AFTER_POWER_FAIL; + reg8 &= ~SLEEP_AFTER_POWER_FAIL; else - reg32 |= SLEEP_AFTER_POWER_FAIL; - write32p(gen_pmcon1, reg32); + reg8 |= SLEEP_AFTER_POWER_FAIL; + write8(pmcbase + GEN_PMCON_A, reg8); } |