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| author | Won Chung <wonchung@google.com> | 2023-04-10 20:52:55 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-08 13:12:41 +0000 |
| commit | af879f2d34207b99bbb62e49a6e1bdcec4e217f4 (patch) | |
| tree | bcc27d4ed9446d5fb67d69a0bab8bc8bebcf67a4 | |
| parent | 467c88b3a971a364d2013b9e397d9cd6f5bcfdda (diff) | |
| download | coreboot-af879f2d34207b99bbb62e49a6e1bdcec4e217f4.tar.gz | |
mb/google/rex/var/rex0: Correct _PLD values for USB C0
Denote the correct value of ACPI _PLD for USB ports.
The horizontal position of port C0 is incorrectly labelled.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | A0
| | C1
| |
+----------------+
BUG=b:216490477
TEST=emerg-rex coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Id9ed435ca0af131e3bb4538701fc97d78146899f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74366
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/overridetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index ef517df2c4..59147c7ba4 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -278,7 +278,7 @@ chip soc/intel/meteorlake register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi @@ -319,7 +319,7 @@ chip soc/intel/meteorlake register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi |