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authorNikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>2021-03-11 19:29:20 -0600
committerMartin Roth <martinroth@google.com>2021-03-13 02:45:00 +0000
commitb6069537317cd66e72c0d08f50fe826f5f22eb7e (patch)
treecf311cda171769854132ac0cabbfe7961f821713
parentb649d6ac116e0a650f4db93a430686965450eca0 (diff)
downloadcoreboot-b6069537317cd66e72c0d08f50fe826f5f22eb7e.tar.gz
soc/amd/picasso/fsp_params.c: GOP: pass VBIOS pointer to FSP
Pass PCI_VGA_RAM_IMAGE_START as VBIOS image pointer for GOP driver. BUG=b:171234996 BRANCH=Zork Change-Id: I49adcacf2abb914e460fbc87b488a22dca8c8af2 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
-rw-r--r--src/soc/amd/picasso/fsp_params.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 067ce2f280..57e51d5c02 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -9,6 +9,7 @@
#include <soc/soc_util.h>
#include <fsp/api.h>
#include "chip.h"
+#include <device/pci.h>
static void fsps_update_emmc_config(FSP_S_CONFIG *scfg,
const struct soc_amd_picasso_config *cfg)
@@ -179,7 +180,7 @@ static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg,
static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
{
- scfg->vbios_buffer_addr = 0;
+ scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
}
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)