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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-05-05 09:27:42 +0300 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-05-14 12:42:55 +0000 |
| commit | ece06dc2d1b6838c2c24daa6375586908144bef6 (patch) | |
| tree | ab21e512a624b800b22770cd88c4fdaf2fad26a9 | |
| parent | ab368d96d72bb3289963903a10208da9c39bee25 (diff) | |
| download | coreboot-ece06dc2d1b6838c2c24daa6375586908144bef6.tar.gz | |
sb/intel/bd82x6x,ibexpeak: Move UPRWC definition
Locate it with all the other PM IO registers.
Change-Id: I779b2e313c9d8370c66c4adb4f6f4d4cf5b4e7dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 9 |
2 files changed, 10 insertions, 8 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 8155479ebf..8face0649e 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -64,10 +64,6 @@ extern const struct southbridge_usb_port mainboard_usb_ports[14]; void early_usb_init(const struct southbridge_usb_port *portmap); -/* PM I/O Space */ -#define UPRWC 0x3c -#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b @@ -459,6 +455,11 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a + +/* PM I/O Space */ +#define UPRWC 0x3c +#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ + #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 #define PM2_CNT 0x50 // mobile only diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 5371641b6e..c447746eea 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -66,10 +66,6 @@ void pch_enable(struct device *dev); #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -/* PM I/O Space */ -#define UPRWC 0x3c -#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b @@ -440,6 +436,11 @@ void pch_enable(struct device *dev); #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a + +/* PM I/O Space */ +#define UPRWC 0x3c +#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ + #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 #define PM2_CNT 0x50 // mobile only |