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authorAngel Pons <th3fanbus@gmail.com>2021-04-18 23:57:21 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-06-09 05:21:23 +0000
commitaced1f02cf24be5a56a97b75c98c861e57e14595 (patch)
tree20aaa49f8823cd571888b509132deb5d67ede337 /configs
parentfc096888e17c2925955bff601b2baddb3b630373 (diff)
downloadcoreboot-aced1f02cf24be5a56a97b75c98c861e57e14595.tar.gz
sb/intel/lynxpoint: Add SerialIO UART console support
Derived from Broadwell and adapted to follow what soc/intel does. Note that SERIALIO_UART_CONSOLE is meant to be selected from the mainboards which expose a SerialIO UART. UART_FOR_CONSOLE also needs to be set in mainboard Kconfig accordingly. It is possible that some of the UART configuration steps in bootblock are unnecessary. However, some of the steps turn off power management features and others are undocumented: omitting them could cause weird issues. Finally, add a config file to ensure the code gets build-tested. Tested on out-of-tree Compal LA-A992P, SerialIO UART 0 can be used to receive coreboot and SeaBIOS logs. Change-Id: Ifb3460dd50ed03421a38f03c80f91ae9fd604022 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52489 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs')
-rw-r--r--configs/config.google_panther.pch_serialio_uart5
1 files changed, 5 insertions, 0 deletions
diff --git a/configs/config.google_panther.pch_serialio_uart b/configs/config.google_panther.pch_serialio_uart
new file mode 100644
index 0000000000..5f7f4c7745
--- /dev/null
+++ b/configs/config.google_panther.pch_serialio_uart
@@ -0,0 +1,5 @@
+# Configuration used to build-test Lynx Point SerialIO UART console code.
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_BOARD_GOOGLE_PANTHER=y
+CONFIG_SERIALIO_UART_CONSOLE=y
+# CONFIG_DRIVERS_UART_8250IO is not set