diff options
author | Julius Werner <jwerner@chromium.org> | 2018-10-10 15:31:36 -0700 |
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committer | Julius Werner <jwerner@chromium.org> | 2018-10-12 20:14:54 +0000 |
commit | ca52a258822c1c47d533684c5a4cbe5f2b7bd487 (patch) | |
tree | 4017c7a2e999f6a7e58f942a7a789352a6666660 /payloads/libpayload/arch/arm64/cache.c | |
parent | e1b1ec7154e4c41adf4eb6a0e4ebd08a2e938a2c (diff) | |
download | coreboot-ca52a258822c1c47d533684c5a4cbe5f2b7bd487.tar.gz |
libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2
This patch adds the new, faster architectural register accessors to
libpayload that were already added to coreboot in CB:27881. It also
hardcodes the assumption that coreboot payloads run at EL2, which has
already been hardcoded in coreboot with CB:27880 (see rationale there).
This means we can drop all the read_current/write_current stuff which
added a lot of unnecessary helpers to check the current exception level.
This patch breaks payloads that used read_current/write_current
accessors, but it seems unlikely that many payloads deal with this stuff
anyway, and it should be a trivial fix (just replace them with the
respective _el2 versions).
Also add accessors for a couple of more registers that are required to
enable debug mode while I'm here.
Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'payloads/libpayload/arch/arm64/cache.c')
-rw-r--r-- | payloads/libpayload/arch/arm64/cache.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c index 2d42522588..f8c5588472 100644 --- a/payloads/libpayload/arch/arm64/cache.c +++ b/payloads/libpayload/arch/arm64/cache.c @@ -39,7 +39,7 @@ void tlb_invalidate_all(void) { /* TLBIALL includes dTLB and iTLB on systems that have them. */ - tlbiall_current(); + tlbiall_el2(); dsb(); isb(); } @@ -119,7 +119,7 @@ void dcache_invalidate_by_mva(void const *addr, size_t len) void cache_sync_instructions(void) { - uint32_t sctlr = raw_read_sctlr_current(); + uint32_t sctlr = raw_read_sctlr_el2(); if (sctlr & SCTLR_C) dcache_clean_all(); /* includes trailing DSB (assembly) */ else if (sctlr & SCTLR_I) |