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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-05 00:21:49 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-07 14:05:05 +0000 |
| commit | ad8a2a475e2733fd4958f816178040153e8cefd3 (patch) | |
| tree | 96efb934b358aed786c04578fc284c49b649e70f /src/drivers/uart/uart8250reg.h | |
| parent | ec4493f88b1408239a546076c67e74049b4bea86 (diff) | |
| download | coreboot-ad8a2a475e2733fd4958f816178040153e8cefd3.tar.gz | |
drivers/uart/uart8250reg.h: use shifts in constants
The UART8250_FCR_TRIGGER bits are bits 6 and 7 in the register, so
rewrite the mask and constants as constants shifted by 6.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0663c1a641355b7bfb59f41479d17117178fb895
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/drivers/uart/uart8250reg.h')
| -rw-r--r-- | src/drivers/uart/uart8250reg.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h index 170c90eee9..35a6845554 100644 --- a/src/drivers/uart/uart8250reg.h +++ b/src/drivers/uart/uart8250reg.h @@ -30,11 +30,11 @@ #define UART8250_FCR_CLEAR_RCVR BIT(1) /* Clear the RCVR FIFO */ #define UART8250_FCR_CLEAR_XMIT BIT(2) /* Clear the XMIT FIFO */ #define UART8250_FCR_DMA_SELECT BIT(3) /* For DMA applications */ -#define UART8250_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ -#define UART8250_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ -#define UART8250_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ -#define UART8250_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ -#define UART8250_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +#define UART8250_FCR_TRIGGER_MASK (3 << 6) /* Mask for the FIFO trigger range */ +#define UART8250_FCR_TRIGGER_1 (0 << 6) /* Mask for trigger set at 1 */ +#define UART8250_FCR_TRIGGER_4 (1 << 6) /* Mask for trigger set at 4 */ +#define UART8250_FCR_TRIGGER_8 (2 << 6) /* Mask for trigger set at 8 */ +#define UART8250_FCR_TRIGGER_14 (3 << 6) /* Mask for trigger set at 14 */ #define UART8250_LCR 0x03 #define UART8250_LCR_WLS_MSK 0x03 /* character length select mask */ |