summaryrefslogtreecommitdiff
path: root/src/mainboard/google/stout
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2022-11-12 14:51:49 +0100
committerPaul Fagerburg <pfagerburg@chromium.org>2023-02-04 01:42:39 +0000
commitb5df65a9aaee50421913ace6d7a4b35e0ddff676 (patch)
treeaa885e29c4e724f4fb583bca5c93fe1243e95da2 /src/mainboard/google/stout
parent9ce7935b490830a709c62e271bf269801520ec29 (diff)
downloadcoreboot-b5df65a9aaee50421913ace6d7a4b35e0ddff676.tar.gz
mb/*: Replace SNB PCI devices with references from chipset.cb
Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/google/stout')
-rw-r--r--src/mainboard/google/stout/devicetree.cb50
1 files changed, 25 insertions, 25 deletions
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 87d0ed94c8..6710b41ac6 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -27,8 +27,8 @@ chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x1ae0 0xc000 inherit
- device pci 00.0 on end # host bridge
- device pci 02.0 on end # vga controller
+ device ref host_bridge on end # host bridge
+ device ref igd on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing
@@ -55,26 +55,26 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "true"
- device pci 14.0 on end # USB 3.0 Controller
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 19.0 off end # Intel Gigabit Ethernet
- device pci 1a.0 on end # USB2 EHCI #2 (AUO4, BlueTooth)
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #2 (WLAN)
- device pci 1c.2 on end # PCIe Port #3 (Card Reader)
+ device ref xhci on end # USB 3.0 Controller
+ device ref mei1 on end # Management Engine Interface 1
+ device ref mei2 off end # Management Engine Interface 2
+ device ref me_ide_r off end # Management Engine IDE-R
+ device ref me_kt off end # Management Engine KT
+ device ref gbe off end # Intel Gigabit Ethernet
+ device ref ehci2 on end # USB2 EHCI #2 (AUO4, BlueTooth)
+ device ref hda on end # High Definition Audio
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 on end # PCIe Port #2 (WLAN)
+ device ref pcie_rp3 on end # PCIe Port #3 (Card Reader)
register "pcie_aspm[2]" = "0x3"
- device pci 1c.3 off end # PCIe Port #4
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 on end # PCIe Port #6 (LAN)
- device pci 1c.6 off end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1d.0 on end # USB2 EHCI #1 (Camera, WLAN, WWAN)
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on
+ device ref pcie_rp4 off end # PCIe Port #4
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 on end # PCIe Port #6 (LAN)
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref ehci1 on end # USB2 EHCI #1 (Camera, WLAN, WWAN)
+ device ref pci_bridge off end # PCI bridge
+ device ref lpc on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
@@ -84,10 +84,10 @@ chip northbridge/intel/sandybridge
end
end
end # LPC bridge
- device pci 1f.2 on end # SATA Controller 1 (HDD/SSD)
- device pci 1f.3 on end # SMBus Controller
- device pci 1f.5 off end # SATA Controller 2 (MSATA)
- device pci 1f.6 off end # Thermal
+ device ref sata1 on end # SATA Controller 1 (HDD/SSD)
+ device ref smbus on end # SMBus Controller
+ device ref sata2 off end # SATA Controller 2 (MSATA)
+ device ref thermal off end # Thermal
end
end
end