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author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-03 11:44:22 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2019-06-06 18:51:03 +0000 |
commit | 4ee83b2f9435fe08cb73ba818b567597cafd973d (patch) | |
tree | 3a0d2a58b62ac87d990703926aaf82d8347d5d49 /src/soc/amd/common/block/acpi/acpi.c | |
parent | 3ce0360592f036ce586a49db84146d435a23e662 (diff) | |
download | coreboot-4ee83b2f9435fe08cb73ba818b567597cafd973d.tar.gz |
soc/amd/stoneyridge: Relocate MMIO access of ACPI registers
The AcpiMmio block allowing direct access to the ACPI registers
has remained consistent across AMD models. Move the support from
soc//stoneyridge to soc//common.
BUG=b:131682806
Change-Id: I0e017a71f8efb4b614986cb327de398644599853
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32655
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/block/acpi/acpi.c')
-rw-r--r-- | src/soc/amd/common/block/acpi/acpi.c | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 200b3c12f5..39e03e2c0c 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -14,9 +14,14 @@ */ #include <arch/acpi.h> +#include <cbmem.h> +#include <elog.h> +#include <console/console.h> #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/acpi.h> #include <halt.h> +#include <security/vboot/vboot_common.h> void poweroff(void) { @@ -31,3 +36,142 @@ void poweroff(void) if (!ENV_SMM) halt(); } + +static uint16_t reset_pm1_status(void) +{ + uint16_t pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS); + acpi_write16(MMIO_ACPI_PM1_STS, pm1_sts); + return pm1_sts; +} + +static void print_num_status_bits(int num_bits, uint32_t status, + const char *const bit_names[]) +{ + int i; + + if (!status) + return; + + for (i = num_bits - 1; i >= 0; i--) { + if (status & (1 << i)) { + if (bit_names[i]) + printk(BIOS_DEBUG, "%s ", bit_names[i]); + else + printk(BIOS_DEBUG, "BIT%d ", i); + } + } +} + +static uint16_t print_pm1_status(uint16_t pm1_sts) +{ + static const char *const pm1_sts_bits[16] = { + [0] = "TMROF", + [4] = "BMSTATUS", + [5] = "GBL", + [8] = "PWRBTN", + [10] = "RTC", + [14] = "PCIEXPWAK", + [15] = "WAK", + }; + + if (!pm1_sts) + return 0; + + printk(BIOS_DEBUG, "PM1_STS: "); + print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return pm1_sts; +} + +static void log_pm1_status(uint16_t pm1_sts) +{ + if (!CONFIG(ELOG)) + return; + + if (pm1_sts & WAK_STS) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, + acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5); + + if (pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + if (pm1_sts & RTC_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + if (pm1_sts & PCIEXPWAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); +} + +static void save_sws(uint16_t pm1_status) +{ + struct soc_power_reg *sws; + uint32_t reg32; + uint16_t reg16; + + sws = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(struct soc_power_reg)); + if (sws == NULL) + return; + sws->pm1_sts = pm1_status; + sws->pm1_en = acpi_read16(MMIO_ACPI_PM1_EN); + reg32 = acpi_read32(MMIO_ACPI_GPE0_STS); + acpi_write32(MMIO_ACPI_GPE0_STS, reg32); + sws->gpe0_sts = reg32; + sws->gpe0_en = acpi_read32(MMIO_ACPI_GPE0_EN); + reg16 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); + reg16 &= SLP_TYP; + sws->wake_from = reg16 >> SLP_TYP_SHIFT; +} + +void acpi_clear_pm1_status(void) +{ + uint16_t pm1_sts = reset_pm1_status(); + + save_sws(pm1_sts); + log_pm1_status(pm1_sts); + print_pm1_status(pm1_sts); +} + +int vboot_platform_is_resuming(void) +{ + if (!(acpi_read16(MMIO_ACPI_PM1_STS) & WAK_STS)) + return 0; + + uint16_t pm_cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); + return acpi_sleep_from_pm1(pm_cnt) == ACPI_S3; +} + +/* If a system reset is about to be requested, modify the PM1 register so it + * will never be misinterpreted as an S3 resume. */ +void set_pm1cnt_s5(void) +{ + uint16_t pm1; + + pm1 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); + pm1 &= ~SLP_TYP; + pm1 |= SLP_TYP_S5 << SLP_TYP_SHIFT; + acpi_write16(MMIO_ACPI_PM1_CNT_BLK, pm1); +} + +void vboot_platform_prepare_reboot(void) +{ + set_pm1cnt_s5(); +} + +void acpi_enable_sci(void) +{ + uint32_t pm1; + + pm1 = acpi_read32(MMIO_ACPI_PM1_CNT_BLK); + pm1 |= ACPI_PM1_CNT_SCIEN; + acpi_write32(MMIO_ACPI_PM1_CNT_BLK, pm1); +} + +void acpi_disable_sci(void) +{ + uint32_t pm1; + + pm1 = acpi_read32(MMIO_ACPI_PM1_CNT_BLK); + pm1 &= ~ACPI_PM1_CNT_SCIEN; + acpi_write32(MMIO_ACPI_PM1_CNT_BLK, pm1); +} |