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| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2021-10-20 23:56:18 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-22 01:28:06 +0000 |
| commit | e8601f47772c9a71486e15e19c2cdd2947034b49 (patch) | |
| tree | 59d08d9155775b513579adddef3610318ef58737 /src/soc/intel/braswell/include | |
| parent | 37e160efb5973ebe7b8b3f5e445d3bdf33c35dd5 (diff) | |
| download | coreboot-e8601f47772c9a71486e15e19c2cdd2947034b49.tar.gz | |
soc/intel/braswell: use mp_cpu_bus_init
Implement mp_init_cpus and use mp_cpu_bus_init as init function in
cpu_bus_ops.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2adcb1e1d79ced804925c81095cc5c0c2e6f9948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/include')
| -rw-r--r-- | src/soc/intel/braswell/include/soc/ramstage.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index 9312b920fc..a1a2ea54c0 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -83,7 +83,6 @@ enum { * initialization, but it's after console and cbmem has been reinitialized. */ void soc_init_pre_device(struct soc_intel_braswell_config *config); -void soc_init_cpus(struct device *dev); void southcluster_enable_dev(struct device *dev); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); int SocStepping(void); |