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authorPraveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>2018-10-23 02:43:05 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-10-25 09:26:50 +0000
commitb66757fc58b9bd025148d9db690009dec487fd0d (patch)
tree419a761bf317a4c56068309e997248d9a75fe8cf /src/soc/intel/common/block/cpu/car/exit_car_fsp.S
parentac6a5080ecb0288c980493cec8e43be2b7490aa3 (diff)
downloadcoreboot-b66757fc58b9bd025148d9db690009dec487fd0d.tar.gz
soc/intel: Consolidate FSP CAR setup and teardown code
This patch adds following changes, - APL, CFL, DENVERTON soc's using same implementation to setup and teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is cosolidated into one file and moved to common code CPU car folder. - exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file and moved to common CPU car. - The new file apollolake/fspcar.c is addded to pass tempraminit parameters. - Coffee lake Soc uses FSPT to support Intel Security features like BootGuard verify boot and Measured boot. Add FSP CAR support for CFL by programming tempraminit parameters and add FSP_T_XIP default if FSP_CAR is selected. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup. Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR without errors. Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9 Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/block/cpu/car/exit_car_fsp.S')
-rw-r--r--src/soc/intel/common/block/cpu/car/exit_car_fsp.S38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/car/exit_car_fsp.S b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S
new file mode 100644
index 0000000000..4ac580ce6f
--- /dev/null
+++ b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cr.h>
+
+/*
+ * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.
+ * This version of chipset_teardown_car sets up the stack, then bypasses
+ * the rest of arch/x86/exit_car.S and calls main() itself instead of
+ * returning to _start. In main(), the TempRamExit FSP API is called
+ * to tear down the CAR and set up caching which can be overwritten
+ * after the API call. More info can be found in the FSP Integration
+ * Guide included with the FSP binary.
+ */
+
+.text
+.global chipset_teardown_car
+chipset_teardown_car:
+
+ /* Set up new stack. */
+ mov post_car_stack_top, %esp
+
+ /* Call C code */
+ call main