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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-16 02:57:30 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-11 12:28:52 +0000 |
| commit | 06e33226b3cfd2c642f769440b7d1b5191c99d6b (patch) | |
| tree | 4b4f072335758951e06d997ec60782d8240069c7 /src/soc/intel/quark/include/soc/ramstage.h | |
| parent | b1c57d1bebb6dd516afa2e85a3f8082a6c77f8ec (diff) | |
| download | coreboot-06e33226b3cfd2c642f769440b7d1b5191c99d6b.tar.gz | |
mb/intel/galileo: Drop the FSP1.1 option
This board is EOL and has FSP2.0 support, so drop the older
version.
Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/quark/include/soc/ramstage.h')
| -rw-r--r-- | src/soc/intel/quark/include/soc/ramstage.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 821f43e218..da2eb61557 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -20,15 +20,9 @@ #include <arch/cpu.h> #include <chip.h> #include <device/device.h> -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -#include <fsp/ramstage.h> -#endif #include <soc/QuarkNcSocId.h> void mainboard_gpio_i2c_init(struct device *dev); -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) -void fsp_silicon_init(bool s3wake); -#endif asmlinkage void chipset_teardown_car(void); #endif /* _SOC_RAMSTAGE_H_ */ |