diff options
author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-29 21:12:27 +0200 |
---|---|---|
committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-10-17 12:59:17 +0000 |
commit | 9034689ee7b8e73cb524006de9538e7daf077c49 (patch) | |
tree | 0679e1a9957576ae6880b0f227d008e3653fc175 /src/soc/intel/tigerlake/acpi.c | |
parent | fbcfb63b06ad5cafc97ce76f8640e5c39b41736d (diff) | |
download | coreboot-9034689ee7b8e73cb524006de9538e7daf077c49.tar.gz |
soc/intel: deduplicate acpi_fill_soc_wake
The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific
handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in
common code.
Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/tigerlake/acpi.c')
-rw-r--r-- | src/soc/intel/tigerlake/acpi.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 1a8ccb9e93..e560f11f69 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -275,21 +275,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; |