diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-05-06 14:37:22 +0300 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-05-14 12:42:45 +0000 |
| commit | ab368d96d72bb3289963903a10208da9c39bee25 (patch) | |
| tree | 0ca3422b6161a3e7df03d4521312ea26ed053bc2 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | 23d4614d8a7c259dd8fae56d7a3627079dc82381 (diff) | |
| download | coreboot-ab368d96d72bb3289963903a10208da9c39bee25.tar.gz | |
sb/intel/lynxpoint: Remove GPE0_{EN,STS}_2 defines
By ACPI specification, those follow GPE0_EN bits in the register space.
Use sizeof() to replace the 2/4 offset previously used.
Change-Id: I27ada0b19b2cf5e8eca71f48bf103dcab1b3cc11
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
0 files changed, 0 insertions, 0 deletions