diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-10 17:12:05 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2021-06-21 08:11:11 +0000 |
| commit | d21b463fb058deccef3a2c2ad80d771b5aba9f19 (patch) | |
| tree | fdb4d134ffe185f67500f3419960996f0cbb8679 /src/southbridge/intel/common/finalize.c | |
| parent | 44a4c0a58dd4ef725c7ff24f9889b12d42a4c5f2 (diff) | |
| download | coreboot-d21b463fb058deccef3a2c2ad80d771b5aba9f19.tar.gz | |
security/intel: Add option to enable SMM flash access only
On platforms where the boot media can be updated externally, e.g.
using a BMC, add the possibility to enable writes in SMM only. This
allows to protect the BIOS region even without the use of vboot, but
keeps SMMSTORE working for use in payloads. Note that this breaks
flashconsole, since the flash becomes read-only.
Tested on Asrock B85M Pro4 and HP 280 G2, SMM BIOS write protection
works as expected, and SMMSTORE can still be used.
Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel/common/finalize.c')
| -rw-r--r-- | src/southbridge/intel/common/finalize.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 975d839e67..6fb27bbb4b 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -45,6 +45,9 @@ void intel_pch_finalize_smm(void) pci_write_config32(PCI_DEV(0, 27, 0), 0x74, pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); + if (CONFIG(BOOTMEDIA_SMM_BWP)) + write_pmbase16(SMI_EN, read_pmbase16(SMI_EN) | TCO_EN); + write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK); post_code(POST_OS_BOOT); |