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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-14 17:46:30 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-17 07:44:25 +0000 |
| commit | 806b2cd42b94b548a5bfa69a7e9c0cf2fda20f7f (patch) | |
| tree | 6e87c9c5d56cab57a78c2671a69d4d1224260b50 /src/southbridge/intel/common/pmutil.c | |
| parent | 95932ba9b7bb1ad1f81cb4a5d16b9fd9c203b254 (diff) | |
| download | coreboot-806b2cd42b94b548a5bfa69a7e9c0cf2fda20f7f.tar.gz | |
sb/intel/common: Fix GPE0 related register conflict
When ACPI GPE0 block was extended to 64 events or 8 bytes,
ACPI PM register space was slightly modified. After
adjustment, PM2_CNT register moved to 0x50 where register
SS_CNT was previously defined to be.
For platforms that have a valid use for PM2_CNT==0x50 in
their FADT, remove overlapping definition of SS_CNT.
On i82801dx/gx ACPI GPE0 supports 32 events, reset_gpe0_status()
incorrectly addressed also GPE0_EN register. For a bit cleaner
implementation, define GPE0_HAS_64_EVENTS.
Change-Id: Iec83e9010146ebd487a61f542ac5c6f4c6a60833
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/common/pmutil.c')
| -rw-r--r-- | src/southbridge/intel/common/pmutil.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index a43b95c69f..8ecb74c371 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -73,6 +73,7 @@ void dump_smi_status(u32 smi_sts) { printk(BIOS_DEBUG, "SMI_STS: "); if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); @@ -100,13 +101,15 @@ void dump_smi_status(u32 smi_sts) */ u64 reset_gpe0_status(void) { - u32 reg_h, reg_l; + u32 reg_h = 0, reg_l; reg_l = read_pmbase32(GPE0_STS); - reg_h = read_pmbase32(GPE0_STS + 4); + if (GPE0_HAS_64_EVENTS) + reg_h = read_pmbase32(GPE0_STS + 4); /* set status bits are cleared by writing 1 to them */ write_pmbase32(GPE0_STS, reg_l); - write_pmbase32(GPE0_STS + 4, reg_h); + if (GPE0_HAS_64_EVENTS) + write_pmbase32(GPE0_STS + 4, reg_h); return (((u64)reg_h) << 32) | reg_l; } @@ -128,7 +131,7 @@ void dump_gpe0_status(u64 gpe0_sts) if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "USB5 "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97/USB5 "); if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); |