diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-04-14 10:17:54 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-04-17 08:14:29 +0000 |
| commit | dc2285bc052e38f0dd3ae43e2aad8cd602837fb4 (patch) | |
| tree | 7e44994276c5a06015cc72548cfc4df26d8eaa7a /src/southbridge/intel/i82371eb | |
| parent | d521b967c435ca22667d8209d7afd5a6b8090601 (diff) | |
| download | coreboot-dc2285bc052e38f0dd3ae43e2aad8cd602837fb4.tar.gz | |
sb/intel: Use ACPI_FADT_C2/C3_NOT_SUPPORTED defines
Change-Id: I242e05ee63f46bedbab3a425e922e60f1c749a15
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/i82371eb')
| -rw-r--r-- | src/southbridge/intel/i82371eb/fadt.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 1d640f4e41..fc3258ae9b 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -36,8 +36,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 4; - fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ - fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ |