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author | Angel Pons <th3fanbus@gmail.com> | 2021-01-26 19:18:09 +0100 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-27 21:28:18 +0000 |
commit | e2ec60f28b06c17c6d1c5c3ecf01ae5cefb4d9a6 (patch) | |
tree | 0d1bf97618d4dfbc07f01d78b0c7b9d8fad6da57 /src/southbridge/intel/lynxpoint/acpi/lpc.asl | |
parent | cbd5bb9cc755ad406e7e13572ff104af1f8b269d (diff) | |
download | coreboot-e2ec60f28b06c17c6d1c5c3ecf01ae5cefb4d9a6.tar.gz |
nb/intel/haswell/haswell.h: Do not include `pch.h`
Avoid indirect header inclusion, include `pch.h` where necessary.
Change-Id: I6b72976a28ffaad68bcf558c8a13b5c221070522
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/acpi/lpc.asl')
-rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/lpc.asl | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index a823b7084b..2e230ea47d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -2,6 +2,8 @@ // Intel LPC Bus Device - 0:1f.0 +#include <southbridge/intel/lynxpoint/pch.h> + Device (LPCB) { Name (_ADR, 0x001f0000) |