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| author | Nico Huber <nico.h@gmx.de> | 2018-10-10 22:44:20 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-22 08:35:08 +0000 |
| commit | 33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (patch) | |
| tree | 0d4c9dfb483b0bdea6aa490bede17a6051337335 /src/southbridge/intel | |
| parent | 73c11194b0ea6a4fb93456fdff36cbd91838d4ec (diff) | |
| download | coreboot-33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31.tar.gz | |
arch/x86: Implement common CF9 reset
It's very common across many x86 silicon vendors, so place it in
`arch/x86/`.
Change-Id: I06c27afa31e5eecfdb7093c02f703bdaabf0594c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions