diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-08 11:31:19 +0300 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-22 14:16:38 +0000 |
commit | 682613f0653064eeeba2b4d15f6d50e32a692bd3 (patch) | |
tree | f53d9721eab49251b9ffda596f2b6d62e239e31d /src/southbridge | |
parent | ea6d12a0de8af000fb72a873b63364462f280643 (diff) | |
download | coreboot-682613f0653064eeeba2b4d15f6d50e32a692bd3.tar.gz |
sb,soc/intel: Replace set_ioapic_id() with setup_ioapic()
This adds delivery of PIC/i8259 interrupts via ExtNMI on the
affected platfoms.
Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82371eb/isa.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82801dx/lpc.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 2 | ||||
-rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 2 |
6 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 51d6b07064..ae92ca942a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -44,7 +44,7 @@ static void pch_enable_ioapic(struct device *dev) /* affirm full set of redirection table entries ("write once") */ ioapic_lock_max_vectors(VIO_APIC_VADDR); - set_ioapic_id(VIO_APIC_VADDR, 0x02); + setup_ioapic(VIO_APIC_VADDR, 0x02); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 3d586bdf80..c2411f2b90 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -61,7 +61,7 @@ static void isa_init(struct device *dev) pci_write_config16(dev, XBCS, reg16); /* Set and verify the IOAPIC ID. */ - set_ioapic_id(VIO_APIC_VADDR, ioapic_id); + setup_ioapic(VIO_APIC_VADDR, ioapic_id); if (ioapic_id != get_ioapic_id(VIO_APIC_VADDR)) die("IOAPIC error!\n"); } diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 321c605366..34d93c4800 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -48,7 +48,7 @@ static void i82801dx_enable_ioapic(struct device *dev) pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - set_ioapic_id(VIO_APIC_VADDR, 0x02); + setup_ioapic(VIO_APIC_VADDR, 0x02); ioapic_set_boot_config(VIO_APIC_VADDR, true); } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ababe675a9..794d34acdb 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -33,7 +33,7 @@ */ static void i82801gx_enable_ioapic(struct device *dev) { - set_ioapic_id(VIO_APIC_VADDR, 0x02); + setup_ioapic(VIO_APIC_VADDR, 0x02); } static void i82801gx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index fa53db20f8..01836b1698 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -37,7 +37,7 @@ static void pch_enable_ioapic(struct device *dev) /* affirm full set of redirection table entries ("write once") */ ioapic_lock_max_vectors(VIO_APIC_VADDR); - set_ioapic_id(VIO_APIC_VADDR, 0x01); + setup_ioapic(VIO_APIC_VADDR, 0x01); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 72f6d80977..ea84def99a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -42,7 +42,7 @@ static void pch_enable_ioapic(struct device *dev) else ioapic_lock_max_vectors(VIO_APIC_VADDR); - set_ioapic_id(VIO_APIC_VADDR, 0x02); + setup_ioapic(VIO_APIC_VADDR, 0x02); } |