| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code | Jonathan Zhang | 2023-03-19 | 1 | -0/+4 |
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX | Michael Niewöhner | 2020-05-11 | 1 | -0/+17 |
| * | soc/intel/xeon_sp: Refactor code to allow for additional CPUs types | Andrey Petrov | 2020-03-26 | 1 | -29/+0 |
| * | soc: Remove copyright notices | Patrick Georgi | 2020-03-18 | 1 | -1/+0 |
| * | soc/intel: Add Intel Xeon Scalable Processor support | Jonathan Zhang | 2020-03-06 | 1 | -0/+30 |
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index : delta/coreboot/coreboot.git | |
| review.coreboot.org: coreboot.git |
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