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/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#ifndef _SOC_P2SB_H_
#define _SOC_P2SB_H_
/* PCI config space registers */
#define HPTC_OFFSET 0x60
#define HPTC_ADDR_ENABLE_BIT (1 << 7)
#define PCH_P2SB_EPMASK0 0xB0
#endif /* _SOC_P2SB_H_ */
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